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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml146 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
147 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
148 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
149 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
154 reg = <0x4d 0x80800000 0x00 0x00048000>,
155 <0x4d 0x80e00000 0x00 0x00008000>,
156 <0x4d 0x80f00000 0x00 0x00008000>;
160 ti,sci-proc-ids = <0x03 0xFF>;
171 reg = <0x00 0x64800000 0x00 0x00080000>,
172 <0x00 0x64e00000 0x00 0x0000c000>;
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dti814x_evm.h35 "loadaddr=0x80200000\0" \
36 "fdtaddr=0x80F80000\0" \
37 "rdaddr=0x81000000\0" \
38 "bootfile=/boot/uImage\0" \
39 "fdtfile=\0" \
40 "console=ttyO0,115200n8\0" \
41 "optargs=\0" \
42 "mmcdev=0\0" \
43 "mmcroot=/dev/mmcblk0p2 ro\0" \
44 "mmcrootfstype=ext4 rootwait\0" \
[all …]
H A Dbur_am335x_common.h19 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
29 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
38 * area between 0x402F0400 and 0x4030B800 as a download area and
39 * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
44 #define CONFIG_SPL_TEXT_BASE 0x402F0400
56 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
59 #define CONFIG_SYS_LOAD_ADDR 0x80000000
63 * always, even when we have more. We always start at 0x80000000,
67 #define CONFIG_SYS_SDRAM_BASE 0x80000000
89 * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
[all …]
H A Dti_armv7_common.h26 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
31 #define CONFIG_SYS_LOAD_ADDR 0x82000000
43 "loadaddr=0x82000000\0" \
44 "kernel_addr_r=0x82000000\0" \
45 "fdtaddr=0x88000000\0" \
46 "fdt_addr_r=0x88000000\0" \
47 "rdaddr=0x88080000\0" \
48 "ramdisk_addr_r=0x88080000\0" \
49 "scriptaddr=0x80000000\0" \
50 "pxefile_addr_r=0x80100000\0" \
[all …]
H A Dmx7_common.h27 #define CONFIG_SYS_BOOTM_LEN 0x1000000
32 #define CONFIG_LOADADDR 0x80800000
33 #define CONFIG_SYS_TEXT_BASE 0x87800000
63 #define CONFIG_ARMV7_SECURE_BASE 0x00900000
67 #define CONFIG_CSF_SIZE 0x2000
H A Dqemu-mips.h24 "panic=1\0" \
25 "bootfile=/tftpboot/vmlinux\0" \
26 "load=tftp 80500000 ${u-boot}\0" \
44 #define CONFIG_DRIVER_NE2000_BASE 0xb4000300
49 #define CONFIG_SYS_NS16550_COM1 0xb40003f8
57 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
58 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
59 #define CONFIG_SYS_ATA_DATA_OFFSET 0
60 #define CONFIG_SYS_ATA_REG_OFFSET 0
61 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
[all …]
H A Dti816x_evm.h16 #define CONFIG_ENV_SIZE 0x2000
21 "mtdids=" MTDIDS_DEFAULT "\0" \
22 "mtdparts=" MTDPARTS_DEFAULT "\0" \
26 "fatload mmc 0 ${loadaddr} uImage;" \
36 #define CONFIG_SYS_SDRAM_BASE 0x80000000
42 #define CONFIG_SYS_TIMERBASE 0x4802E000
51 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
63 * access CS0 at is 0x8000000.
65 #define CONFIG_SYS_NAND_BASE 0x8000000
91 #define MTDIDS_DEFAULT "nand0=nand.0"
[all …]
H A Ddbau1x00.h45 "panic=1\0" \
46 "bootfile=/tftpboot/vmlinux.srec\0" \
47 "load=tftp 80500000 ${u-boot}\0" \
52 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
80 #if (CONFIG_SYS_MHZ % 12) != 0
86 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
88 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
90 #define CONFIG_SYS_MEMTEST_START 0x80100000
91 #define CONFIG_SYS_MEMTEST_END 0x80800000
101 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
[all …]
H A Dflea3.h26 #define CONFIG_SYS_TEXT_BASE 0xA0000000
49 #define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe
73 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
80 #define CONFIG_FEC_MXC_PHYADDR 0x1
97 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
98 #define CONFIG_SYS_MEMTEST_END 0x10000
110 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
168 "netdev=eth0\0" \
170 "nfsroot=${serverip}:${rootpath}\0" \
171 "ramargs=setenv bootargs root=/dev/ram rw\0" \
[all …]
H A Dwoodburn_common.h45 #define CONFIG_SYS_SPD_BUS_NUM 0
54 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
59 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
84 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
91 #define CONFIG_FEC_MXC_PHYADDR 0x1
106 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
107 #define CONFIG_SYS_MEMTEST_END 0x10000
180 "netdev=eth0\0" \
182 "nfsroot=${serverip}:${rootpath}\0" \
183 "ramargs=setenv bootargs root=/dev/ram rw\0" \
[all …]
H A Dmx31ads.h17 #define CONFIG_SYS_TEXT_BASE 0xA0000000
48 #define CONFIG_FSL_PMIC_CS 0
58 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
61 "netdev=eth0\0" \
62 "uboot_addr=0xa0000000\0" \
63 "uboot=mx31ads/u-boot.bin\0" \
64 "kernel=mx31ads/uImage\0" \
65 "nfsroot=/opt/eldk/arm\0" \
66 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
68 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
[all …]
H A Dmx35pdk.h24 #define CONFIG_SYS_TEXT_BASE 0xA0000000
54 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
61 #define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
83 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
100 #define CONFIG_FEC_MXC_PHYADDR 0x1F
114 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
115 #define CONFIG_SYS_MEMTEST_END 0x10000
129 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
189 #define CONFIG_MXC_USB_PORT 0
197 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
[all …]
H A Dvexpress_common.h21 #define V2M_PA_CS0 0x40000000
22 #define V2M_PA_CS1 0x44000000
23 #define V2M_PA_CS2 0x48000000
24 #define V2M_PA_CS3 0x4c000000
25 #define V2M_PA_CS7 0x10000000
28 #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
32 #define V2M_BASE 0x60000000
33 #define CONFIG_SYS_TEXT_BASE 0x60800000
36 #define V2M_PA_CS0 0x08000000
37 #define V2M_PA_CS1 0x0c000000
[all …]
/OK3568_Linux_fs/kernel/arch/s390/kernel/
H A Duprobes.c42 return 0; in arch_uprobe_pre_xol()
58 return 0; in check_per_event()
60 if (control == 0) in check_per_event()
63 if ((control & 0x20200000) && (cause & 0x2000)) in check_per_event()
65 if (cause & 0x8000) { in check_per_event()
67 if ((control & 0x80800000) == 0x80000000) in check_per_event()
70 if (((control & 0x80800000) == 0x80800000) && in check_per_event()
75 return 0; in check_per_event()
91 int reg = (auprobe->insn[0] & 0xf0) >> 4; in arch_uprobe_post_xol()
96 int ilen = insn_length(auprobe->insn[0] >> 8); in arch_uprobe_post_xol()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A DMakefile.boot2 zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX) += 0xc0008000
3 params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0000100
4 initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0800000
6 zreladdr-$(CONFIG_ARCH_DAVINCI_DMx) += 0x80008000
7 params_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80000100
8 initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80800000
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/include/mach/
H A Dep93xx-regs.h18 #define EP93XX_AHB_PHYS_BASE 0x80000000
19 #define EP93XX_AHB_VIRT_BASE 0xfef00000
20 #define EP93XX_AHB_SIZE 0x00100000
25 #define EP93XX_APB_PHYS_BASE 0x80800000
26 #define EP93XX_APB_VIRT_BASE 0xfed00000
27 #define EP93XX_APB_SIZE 0x00200000
33 #define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
34 #define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
36 #define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000)
37 #define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192e.c36 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
37 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
38 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
39 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
40 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
41 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
42 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
43 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
44 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
45 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dphy.c53 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92ee_phy_query_bb_reg()
143 u8 rfpi_enable = 0; in _rtl92ee_phy_rf_serial_read()
146 offset &= 0xff; in _rtl92ee_phy_rf_serial_read()
150 return 0xFFFFFFFF; in _rtl92ee_phy_rf_serial_read()
176 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92ee_phy_rf_serial_read()
195 offset &= 0xff; in _rtl92ee_phy_rf_serial_write()
197 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92ee_phy_rf_serial_write()
200 "RFW-%d Addr[0x%x]=0x%x\n", rfpath, in _rtl92ee_phy_rf_serial_write()
227 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92ee_phy_bb_config()
234 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92ee_phy_bb_config()
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.ubispl60 #define SPL_FINFO_ADDR 0x80800000
61 #define SPL_DTB_LOAD_ADDR 0x81800000
62 #define SPL_KERNEL_LOAD_ADDR 0x82000000
68 .vol_id = 0, /* kernel volume */
91 * part_spl { .start = 0, .end = 4 }
H A DREADME.qemu-mips67 # tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" …
83 ide4 : start= 0, size= 0, Id= 0
105 setenv rd_start 0x80800000
113 setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
115 setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
116 setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
160 64 RVECENT(reset,0) /* U-Boot entry point */
163 Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
171 $1 = 0x87fa0000
176 U-Boot relocates itself to 0x87fa0000 by default.
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h25 #define EP93XX_AHB_BASE 0x80000000
26 #define EP93XX_APB_BASE 0x80800000
29 * 0x80000000 - 0x8000FFFF: DMA
31 #define DMA_OFFSET 0x000000
74 * 0x80010000 - 0x8001FFFF: Ethernet MAC
76 #define MAC_OFFSET 0x010000
156 #define SELFCTL_RESET (1 << 0)
187 #define BMCTL_RXEN (1 << 0)
192 #define BMSTS_QID_MASK 0x07
193 #define BMSTS_QID_RXDATA 0x00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dphy.c91 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl8723be_phy_mac_config()
106 regval | BIT(13) | BIT(0) | BIT(1)); in rtl8723be_phy_bb_config()
112 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl8723be_phy_bb_config()
113 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl8723be_phy_bb_config()
115 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723be_phy_bb_config()
120 crystalcap = crystalcap & 0x3F; in rtl8723be_phy_bb_config()
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl8723be_phy_bb_config()
140 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); in _rtl8723be_check_positive()
142 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ in _rtl8723be_check_positive()
150 0 << 20 | /* interface 2/2 */ in _rtl8723be_check_positive()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8188eu/hal/
H A Dphy.c25 for (i = 0; i <= 31; i++) { in cal_bit_shift()
26 if (((bitmask >> i) & 0x1) == 1) in cal_bit_shift()
56 u32 ret = 0; in rf_serial_read()
59 u8 rfpi_enable = 0; in rf_serial_read()
61 offset &= 0xff; in rf_serial_read()
100 u32 data_and_addr = 0; in rf_serial_write()
103 offset &= 0xff; in rf_serial_write()
104 data_and_addr = ((offset << 20) | (data & 0x000fffff)) & 0x0fffffff; in rf_serial_write()
138 u8 TxCount = 0, path_nums; in get_tx_power_index()
142 for (TxCount = 0; TxCount < path_nums; TxCount++) { in get_tx_power_index()
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/fpsp040/
H A Dstanh.S69 BOUNDS1: .long 0x3FD78000,0x3FFFDDCE | ... 2^(-40), (5/2)LOG2
90 andl #0x7FFFFFFF,%d0
99 andl #0x7FFF0000,%d0
100 addl #0x00010000,%d0 | ...EXPONENT OF 2|X|
102 andl #0x80000000,SGN(%a6)
112 fadds #0x40000000,%fp1 | ...Z+2
122 cmpl #0x3FFF8000,%d0
125 cmpl #0x40048AA1,%d0
134 andl #0x7FFF0000,%d0
135 addl #0x00010000,%d0 | ...EXPO OF 2|X|
[all …]

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