Searched +full:0 +full:x8006a000 (Results 1 – 6 of 6) sorted by relevance
86 reg = <0x8006a000 0x2000>;
7 If a channel is empty/reserved, 0 should be filled in place.21 reg = <0x80004000 0x2000>;25 87 86 0 0>;36 reg = <0x80024000 0x2000>;37 interrupts = <78 79 66 056 reg = <0x8006a000 0x2000>;
19 ref_xtal 0106 reg = <0x80040000 0x2000>;112 reg = <0x8006a000 0x2000>;
22 #define MXS_ICOLL_BASE 0x8000000023 #define MXS_APBH_BASE 0x8000400024 #define MXS_ECC8_BASE 0x8000800025 #define MXS_BCH_BASE 0x8000A00026 #define MXS_GPMI_BASE 0x8000C00027 #define MXS_SSP0_BASE 0x8001000028 #define MXS_SSP1_BASE 0x8003400029 #define MXS_ETM_BASE 0x8001400030 #define MXS_PINCTRL_BASE 0x8001800031 #define MXS_DIGCTL_BASE 0x8001C000[all …]
41 #size-cells = <0>;44 pinctrl-0 = <&spi2_pins_a>;46 qca7000: ethernet@0 {48 reg = <0x0>;50 interrupts = <25 0x1>; /* Index: 25, rising edge */78 reg = <0x8006a000 0x2000>;80 pinctrl-0 = <&auart0_2pins_a>;
43 #size-cells = <0>;45 cpu@0 {48 reg = <0>;56 reg = <0x80000000 0x80000>;63 reg = <0x80000000 0x3c900>;70 reg = <0x80000000 0x2000>;74 reg = <0x80002000 0x2000>;83 reg = <0x80004000 0x2000>;87 87 86 0 0>;98 reg = <0x80006000 0x800>;[all …]