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/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dsysfb_efi.c30 OVERRIDE_NONE = 0x0,
31 OVERRIDE_BASE = 0x1,
32 OVERRIDE_STRIDE = 0x2,
33 OVERRIDE_HEIGHT = 0x4,
34 OVERRIDE_WIDTH = 0x8,
38 [M_I17] = { "i17", 0x80010000, 1472 * 4, 1440, 900, OVERRIDE_NONE },
39 [M_I20] = { "i20", 0x80010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE }, /* guess */
40 [M_I20_SR] = { "imac7", 0x40010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE },
41 [M_I24] = { "i24", 0x80010000, 2048 * 4, 1920, 1200, OVERRIDE_NONE }, /* guess */
42 [M_I24_8_1] = { "imac8", 0xc0060000, 2048 * 4, 1920, 1200, OVERRIDE_NONE },
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_hwimg_raw_data_8852b.h34 #if 0
39 PW_BYRATE_PARA_OFFS = 0xF
54 PW_BYRATE_RATE_NULL = 0xF
145 0xF0010000, 0x00000000,
146 0xF0020000, 0x00000001,
147 0xF0010001, 0x00000002,
148 0xF0020001, 0x00000003,
149 0xF0030001, 0x00000004,
150 0xF0040001, 0x00000005,
151 0xF0050001, 0x00000006,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_hwimg_raw_data_8852b.h34 #if 0
39 PW_BYRATE_PARA_OFFS = 0xF
54 PW_BYRATE_RATE_NULL = 0xF
145 0xF0010000, 0x00000000,
146 0xF0020000, 0x00000001,
147 0xF0010001, 0x00000002,
148 0xF0020001, 0x00000003,
149 0xF0030001, 0x00000004,
150 0xF0040001, 0x00000005,
151 0xF0050001, 0x00000006,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-base.h22 #define MXS_ICOLL_BASE 0x80000000
23 #define MXS_APBH_BASE 0x80004000
24 #define MXS_ECC8_BASE 0x80008000
25 #define MXS_BCH_BASE 0x8000A000
26 #define MXS_GPMI_BASE 0x8000C000
27 #define MXS_SSP0_BASE 0x80010000
28 #define MXS_SSP1_BASE 0x80034000
29 #define MXS_ETM_BASE 0x80014000
30 #define MXS_PINCTRL_BASE 0x80018000
31 #define MXS_DIGCTL_BASE 0x8001C000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dxlnx,spdif.txt13 - xlnx,spdif-mode: 0 :- receiver mode
24 interrupts = <0 91 4>;
25 reg = <0x0 0x80010000 0x0 0x10000>;
H A Dxlnx,audio-formatter.txt25 interrupts = <0 104 4>, <0 105 4>;
26 reg = <0x0 0x80010000 0x0 0x1000>;
28 clocks = <&clk 71>, <&clk_wiz_1 0>;
/OK3568_Linux_fs/u-boot/configs/
H A Dhuawei_hg556a_ram_defconfig2 CONFIG_SYS_TEXT_BASE=0x80010000
H A Dsagem_f@st1704_ram_defconfig2 CONFIG_SYS_TEXT_BASE=0x80010000
H A Dnetgear_cg3100d_ram_defconfig2 CONFIG_SYS_TEXT_BASE=0x80010000
H A Dcomtrend_ct5361_ram_defconfig2 CONFIG_SYS_TEXT_BASE=0x80010000
H A Dcomtrend_vr3032u_ram_defconfig2 CONFIG_SYS_TEXT_BASE=0x80010000
H A Dsfr_nb4-ser_ram_defconfig2 CONFIG_SYS_TEXT_BASE=0x80010000
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dmxs-spi.yaml50 #size-cells = <0>;
52 reg = <0x80010000 0x2000>;
54 dmas = <&dma_apbh 0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmxs-mmc.yaml53 reg = <0x80010000 2000>;
55 dmas = <&dma_apbh 0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dalphascale,acc.txt22 CLKID_AHB_ROM 0
102 reg = <0x80010000 0x4000>;
110 reg = <0x80088000 0x4000>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
49 shirq: interrupt-controller@0x50000000 {
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dmx31pdk.h31 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
32 #define CONFIG_SYS_TEXT_BASE 0x87e00000
72 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
74 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
75 "bootcmd=run bootcmd_net\0" \
77 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
78 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
79 "nand erase 0x0 0x40000; " \
80 "nand write 0x81000000 0x0 0x40000\0"
83 #define CONFIG_SMC911X_BASE 0xB6000000
[all …]
H A DM5208EVBE.h18 #define CONFIG_SYS_UART_PORT (0)
32 # define CONFIG_SYS_FEC0_PINMUX 0
54 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
55 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
69 "netdev=eth0\0" \
70 "loadaddr=40010000\0" \
71 "u-boot=u-boot.bin\0" \
72 "load=tftp ${loadaddr) ${u-boot}\0" \
73 "upd=run load; run prog\0" \
74 "prog=prot off 0 3ffff;" \
[all …]
H A Dcolibri_vf.h51 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
58 #define CONFIG_FEC_MXC_PHYADDR 0
64 #define CONFIG_LOADADDR 0x80008000
65 #define CONFIG_FDTADDR 0x84000000
68 #define CONFIG_SYS_TEXT_BASE 0x3f408000
72 "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \
75 "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
76 "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
77 "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
80 "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
[all …]
H A Dlegoev3.h30 #define CONFIG_SYS_TEXT_BASE 0xc1080000
35 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
41 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
44 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
58 #define CONFIG_SYS_DV_CLKMODE 0
60 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
61 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
62 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
63 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
64 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
[all …]
H A Dvf610twr.h44 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
51 #define CONFIG_FEC_MXC_PHYADDR 0
66 #define CONFIG_SYS_SPD_BUS_NUM 0
69 #define CONFIG_SYS_LOAD_ADDR 0x82000000
72 #define CONFIG_SYS_TEXT_BASE 0x3f408000
86 "bootm_size=0x07000000\0" \
87 "loadaddr=0x82000000\0" \
88 "kernel_addr_r=0x82000000\0" \
89 "fdt_addr=0x84000000\0" \
90 "fdt_addr_r=0x84000000\0" \
[all …]
H A DM53017EVB.h23 #define CONFIG_SYS_UART_PORT (0)
41 # define CONFIG_SYS_FEC0_PINMUX 0
43 # define CONFIG_SYS_FEC1_PINMUX 0
60 #define CONFIG_SYS_RTC_CNT (0x8000)
71 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
72 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
86 "netdev=eth0\0" \
87 "loadaddr=40010000\0" \
88 "u-boot=u-boot.bin\0" \
89 "load=tftp ${loadaddr) ${u-boot}\0" \
[all …]
H A Dpcm052.h52 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
61 #define CONFIG_FEC_MXC_PHYADDR 0
78 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
82 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
87 #define CONFIG_LOADADDR 0x82000000
90 #define CONFIG_SYS_TEXT_BASE 0x3f408000
117 "autoload=no\0" \
118 "fdt_high=0xffffffff\0" \
119 "initrd_high=0xffffffff\0" \
120 "blimg_file=u-boot.vyb\0" \
[all …]
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Darm_pl180_mmci.h23 #define INIT_PWR 0xBF /* Power on, full power, not open drain */
27 #define SDI_PWR_PWRCTRL_MASK 0x00000003
28 #define SDI_PWR_PWRCTRL_ON 0x00000003
29 #define SDI_PWR_PWRCTRL_OFF 0x00000000
30 #define SDI_PWR_DAT2DIREN 0x00000004
31 #define SDI_PWR_CMDDIREN 0x00000008
32 #define SDI_PWR_DAT0DIREN 0x00000010
33 #define SDI_PWR_DAT31DIREN 0x00000020
34 #define SDI_PWR_OPD 0x00000040
35 #define SDI_PWR_FBCLKEN 0x00000080
[all …]
/OK3568_Linux_fs/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c27 return 0; in checkboard()
42 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, in dram_init()
44 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, in dram_init()
51 __raw_writel(0x33211530, &sdp->cfg1); in dram_init()
52 __raw_writel(0x56570000, &sdp->cfg2); in dram_init()
54 __raw_writel(0xE1462C02, &sdp->ctrl); in dram_init()
57 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
59 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
61 __raw_writel(0x008D0000, &sdp->mode); in dram_init()
63 __raw_writel(0x80010000, &sdp->mode); in dram_init()
[all …]

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