Searched +full:0 +full:x8000c000 (Results 1 – 15 of 15) sorted by relevance
22 #define MXS_ICOLL_BASE 0x8000000023 #define MXS_APBH_BASE 0x8000400024 #define MXS_ECC8_BASE 0x8000800025 #define MXS_BCH_BASE 0x8000A00026 #define MXS_GPMI_BASE 0x8000C00027 #define MXS_SSP0_BASE 0x8001000028 #define MXS_SSP1_BASE 0x8003400029 #define MXS_ETM_BASE 0x8001400030 #define MXS_PINCTRL_BASE 0x8001800031 #define MXS_DIGCTL_BASE 0x8001C000[all …]
114 #size-cells = <0>;116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
20 #define CONFIG_SYS_TEXT_BASE 0x1100000021 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc30 #define CONFIG_SYS_TEXT_BASE 0x0020100031 #define CONFIG_SPL_TEXT_BASE 0xFFFFE00033 #define CONFIG_SPL_RELOC_TEXT_BASE 0x0010000034 #define CONFIG_SPL_RELOC_STACK 0x0010000035 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)36 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)37 #define CONFIG_SYS_NAND_U_BOOT_START 0x0020000038 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0[all …]
25 #define CONFIG_SYS_TEXT_BASE 0xfe00000039 #define CONFIG_SYS_IMMR 0xE000000041 #define CONFIG_SYS_MEMTEST_START 0x0000100042 #define CONFIG_SYS_MEMTEST_END 0x0700000054 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/69 /* 0x80840102 */71 #define CONFIG_SYS_DDR_TIMING_3 0x0000000072 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \73 | (0 << TIMING_CFG0_WRT_SHIFT) \80 /* 0x0e720802 */[all …]
18 #define CONFIG_SYS_TEXT_BASE 0xFE00000073 #define CONFIG_SYS_SICRL 0x0000000080 #define CONFIG_SYS_IMMR 0xE000000085 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */88 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */94 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */104 /* 0x80840102 */105 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \106 | (0 << TIMING_CFG0_WRT_SHIFT) \107 | (0 << TIMING_CFG0_RRT_SHIFT) \[all …]
19 #define CONFIG_SYS_TEXT_BASE 0xFE00000057 #define CONFIG_SYS_SICRL 0x0000000062 #define CONFIG_SYS_IMMR 0xE000000067 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */68 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */69 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */75 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */83 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */91 /* 0x80010101 */92 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \[all …]
43 #define CONFIG_SYS_TEXT_BASE 0xfff8000058 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */59 #define CONFIG_SYS_MEMTEST_END 0x0040000064 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f8000069 #define CONFIG_SYS_CCSRBAR 0xe000000082 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x0000000092 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202[all …]
20 #define CONFIG_SYS_TEXT_BASE 0x1100000021 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc27 #define CONFIG_SYS_TEXT_BASE 0x1100000028 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc34 #define CONFIG_SYS_TEXT_BASE 0x1100000035 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc44 #define CONFIG_SYS_TEXT_BASE 0x0020100045 #define CONFIG_SPL_TEXT_BASE 0xFFFFE00047 #define CONFIG_SPL_RELOC_TEXT_BASE 0x0010000048 #define CONFIG_SPL_RELOC_STACK 0x00100000[all …]
31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff0000034 #define CONFIG_SPL_PAD_TO 0x400037 #define CONFIG_SYS_NAND_U_BOOT_DST 0x0010000038 #define CONFIG_SYS_NAND_U_BOOT_START 0x0010010040 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x0001000041 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)50 #define CONFIG_SYS_TEXT_BASE 0xFE00000083 #define CONFIG_SYS_IMMR 0xE000000089 #define CONFIG_SYS_MEMTEST_START 0x00001000[all …]
24 #define CONFIG_SYS_TEXT_BASE 0xFE00000047 #define CONFIG_SYS_IMMR 0xE000000050 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */51 #define CONFIG_SYS_MEMTEST_END 0x0010000064 #define CONFIG_SYS_SPD_BUS_NUM 065 #define SPD_EEPROM_ADDRESS1 0x5266 #define SPD_EEPROM_ADDRESS2 0x5170 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef84 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/94 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001[all …]
17 #define __SW_BOOT_MASK 0x0318 #define __SW_BOOT_NOR 0xe419 #define __SW_BOOT_SD 0x5425 #define __SW_BOOT_MASK 0x0326 #define __SW_BOOT_NOR 0xe027 #define __SW_BOOT_SD 0x5036 #define __SW_BOOT_MASK 0x0337 #define __SW_BOOT_NOR 0x5c38 #define __SW_BOOT_SPI 0x1c39 #define __SW_BOOT_SD 0x9c[all …]
28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"92 #define CONFIG_SYS_TEXT_BASE 0x1100000093 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc100 #define CONFIG_SYS_TEXT_BASE 0x11000000101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc105 #define CONFIG_SYS_TEXT_BASE 0xeff80000107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */140 #define CONFIG_SYS_MEMTEST_END 0x1fffffff[all …]
32 #size-cells = <0>;34 cpu@0 {37 reg = <0>;45 reg = <0x80000000 0x80000>;52 reg = <0x80000000 0x40000>;59 reg = <0x80000000 0x2000>;64 reg = <0x80004000 0x2000>;65 interrupts = <0 14 20 075 reg = <0x80008000 0x2000>;83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;[all …]
43 #size-cells = <0>;45 cpu@0 {48 reg = <0>;56 reg = <0x80000000 0x80000>;63 reg = <0x80000000 0x3c900>;70 reg = <0x80000000 0x2000>;74 reg = <0x80002000 0x2000>;83 reg = <0x80004000 0x2000>;87 87 86 0 0>;98 reg = <0x80006000 0x800>;[all …]
138 0x80000000 | 0xf0000000 | UART0139 0x80004000 | 0xf0004000 | UART1140 0x80008000 | 0xf0008000 | UART2141 0x8000c000 | 0xf000c000 | UART3142 0x80010000 | 0xf0010000 | UART4143 0x80014000 | 0xf0014000 | UART5144 0x80018000 | 0xf0018000 | UART6145 0x8001c000 | 0xf001c000 | UART7146 0x80020000 | 0xf0020000 | UART8147 0x80024000 | 0xf0024000 | UART9[all …]