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/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dsun3x.h6 #define SUN3X_IOMMU 0x60000000
7 #define SUN3X_ENAREG 0x61000000
8 #define SUN3X_INTREG 0x61001400
9 #define SUN3X_DIAGREG 0x61001800
10 #define SUN3X_ZS1 0x62000000
11 #define SUN3X_ZS2 0x62002000
12 #define SUN3X_LANCE 0x65002000
13 #define SUN3X_EEPROM 0x64000000
14 #define SUN3X_IDPROM 0x640007d8
15 #define SUN3X_VIDEO_BASE 0x50000000
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H A Dsun3xprom.h18 #define SUN3X_IOMMU 0x60000000
19 #define SUN3X_ENAREG 0x61000000
20 #define SUN3X_INTREG 0x61001400
21 #define SUN3X_DIAGREG 0x61001800
22 #define SUN3X_ZS1 0x62000000
23 #define SUN3X_ZS2 0x62002000
24 #define SUN3X_LANCE 0x65002000
25 #define SUN3X_EEPROM 0x64000000
26 #define SUN3X_IDPROM 0x640007d8
27 #define SUN3X_VIDEO_BASE 0x50400000
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/OK3568_Linux_fs/u-boot/include/configs/
H A Drv1108_common.h16 #define CONFIG_SYS_SDRAM_BASE 0x60000000
17 #define SDRAM_MAX_SIZE 0x80000000
18 #define CONFIG_SYS_TEXT_BASE 0x60000000
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x200000)
20 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
23 #define CONFIG_SPL_STACK 0x10080700
24 #define CONFIG_SPL_TEXT_BASE 0x10080800
25 #define CONFIG_SPL_MAX_SIZE 0x4000
28 #define CONFIG_SPL_BSS_MAX_SIZE 0x100
30 #define CONFIG_ROCKUSB_G_DNL_PID 0x110A
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H A Drk3036_common.h21 #define CONFIG_SYS_TEXT_BASE 0x60200000
22 #define CONFIG_SYS_INIT_SP_ADDR 0x60400000
23 #define CONFIG_SYS_LOAD_ADDR 0x61800800
24 #define CONFIG_SPL_TEXT_BASE 0x60000000
26 #define CONFIG_TPL_STACK 0x10081fff
27 #define CONFIG_TPL_TEXT_BASE 0x10081000
31 #define CONFIG_ROCKUSB_G_DNL_PID 0x301A
36 #define CONFIG_SYS_SDRAM_BASE 0x60000000
38 #define SDRAM_MAX_SIZE 0x80000000
51 "scriptaddr1=0x60000000\0" \
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H A Dve8313.h25 #define CONFIG_SYS_TEXT_BASE 0xfe000000
39 #define CONFIG_SYS_IMMR 0xE0000000
41 #define CONFIG_SYS_MEMTEST_START 0x00001000
42 #define CONFIG_SYS_MEMTEST_END 0x07000000
54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
69 /* 0x80840102 */
71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
73 | (0 << TIMING_CFG0_WRT_SHIFT) \
80 /* 0x0e720802 */
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/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
/OK3568_Linux_fs/u-boot/post/lib_powerpc/
H A Dcpu_asm.h10 #define BIT_C 0x00000001
12 #define OP_BLR 0x4e800020
13 #define OP_EXTSB 0x7c000774
14 #define OP_EXTSH 0x7c000734
15 #define OP_NEG 0x7c0000d0
16 #define OP_CNTLZW 0x7c000034
17 #define OP_ADD 0x7c000214
18 #define OP_ADDC 0x7c000014
19 #define OP_ADDME 0x7c0001d4
20 #define OP_ADDZE 0x7c000194
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi.yaml46 <bank-number> 0 <address of the bank> <size>
49 "^.*@[0-4],[a-f0-9]+$":
59 0: Asynchronous mode 1 SRAM/FRAM.
72 minimum: 0
123 enum: [ 0, 128, 256, 512, 1024 ]
124 default: 0
183 reaches 0, the controller splits the current access, toggles NE to
208 reg = <0x58002000 0x1000>;
212 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
213 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr4-100.dtsi6 0x2
7 0xa
8 0x3
9 0x2
10 0x1
11 0x0
12 0xf
13 0xf
14 0
15 0
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/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h36 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
37 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
38 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
39 #define DAVINCI_UART0_BASE (0x01c20000)
40 #define DAVINCI_UART1_BASE (0x01c20400)
41 #define DAVINCI_TIMER3_BASE (0x01c20800)
42 #define DAVINCI_I2C_BASE (0x01c21000)
43 #define DAVINCI_TIMER0_BASE (0x01c21400)
44 #define DAVINCI_TIMER1_BASE (0x01c21800)
45 #define DAVINCI_WDOG_BASE (0x01c21c00)
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/via/
H A Daccel.c19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
35 return 0; in viafb_set_bpp()
44 u32 ge_cmd = 0, tmp, i; in hw_bitblt_1()
54 ge_cmd |= 0x00008000; in hw_bitblt_1()
59 ge_cmd |= 0x00004000; in hw_bitblt_1()
67 case 0x00: /* blackness */ in hw_bitblt_1()
68 case 0x5A: /* pattern inversion */ in hw_bitblt_1()
69 case 0xF0: /* pattern copy */ in hw_bitblt_1()
70 case 0xFF: /* whiteness */ in hw_bitblt_1()
84 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000) in hw_bitblt_1()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_srv.c65 #define DMUB_CW0_BASE (0x60000000)
66 #define DMUB_CW1_BASE (0x61000000)
67 #define DMUB_CW3_BASE (0x63000000)
68 #define DMUB_CW4_BASE (0x64000000)
69 #define DMUB_CW5_BASE (0x65000000)
70 #define DMUB_CW6_BASE (0x66000000)
89 for (pos = 0; pos < end; pos += sizeof(buf)) in dmub_flush_buffer_mem()
102 uint32_t blob_size = 0; in dmub_get_fw_meta_info()
103 uint32_t meta_offset = 0; in dmub_get_fw_meta_info()
114 meta_offset = 0; in dmub_get_fw_meta_info()
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dowl-mmc.c27 #define OWL_REG_SD_EN 0x0000
28 #define OWL_REG_SD_CTL 0x0004
29 #define OWL_REG_SD_STATE 0x0008
30 #define OWL_REG_SD_CMD 0x000c
31 #define OWL_REG_SD_ARG 0x0010
32 #define OWL_REG_SD_RSPBUF0 0x0014
33 #define OWL_REG_SD_RSPBUF1 0x0018
34 #define OWL_REG_SD_RSPBUF2 0x001c
35 #define OWL_REG_SD_RSPBUF3 0x0020
36 #define OWL_REG_SD_RSPBUF4 0x0024
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
94 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
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/OK3568_Linux_fs/kernel/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
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/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
79 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
80 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
85 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
89 (((uintptr_t)(i) & 0x8000) >> 15))
211 #define PPC_INST_BCCTR_FLUSH 0x4c400420
212 #define PPC_INST_COPY 0x7c20060c
213 #define PPC_INST_DCBA 0x7c0005ec
214 #define PPC_INST_DCBA_MASK 0xfc0007fe
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/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c31 #define AR5008_11NA_OFDM_SHIFT 0
55 {0x000098b0, 0x1e5795e5},
56 {0x000098e0, 0x02008020},
61 {0x000098b0, 0x02108421},
62 {0x000098ec, 0x00000008},
67 {0x000098b0, 0x0e73ff17},
68 {0x000098e0, 0x00000420},
73 {0x000098f0, 0x01400018, 0x01c00018},
78 {0x0000989c, 0x00000500},
79 {0x0000989c, 0x00000800},
[all …]
H A Dar9003_phy.c27 #define AR9300_11NA_OFDM_SHIFT 0
38 /* level: 0 1 2 3 4 5 6 7 8 */
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
42 /* level: 0 1 2 3 4 5 6 7 8 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
142 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
146 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
151 u16 bMode, fracMode = 0, aModeRefSel = 0; in ar9003_hw_set_channel()
152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #clock-cells = <0>;
81 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram-rk3399-lpddr4-400.inc5 .rank = 0x2,
6 .col = 0xA,
7 .bk = 0x3,
8 .bw = 0x2,
9 .dbw = 0x1,
10 .row_3_4 = 0x0,
11 .cs0_row = 0xF,
12 .cs1_row = 0xF,
13 .cs0_high16bit_row = 0xF,
14 .cs1_high16bit_row = 0xF,
[all …]
H A Dsdram-rk3399-lpddr4-800.inc5 .rank = 0x2,
6 .col = 0xA,
7 .bk = 0x3,
8 .bw = 0x2,
9 .dbw = 0x1,
10 .row_3_4 = 0x0,
11 .cs0_row = 0xF,
12 .cs1_row = 0xF,
13 .cs0_high16bit_row = 0xF,
14 .cs1_high16bit_row = 0xF,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/rtl8822c/
H A Dhalhwimg8822c_bb.c30 #define CUT_DONT_CARE 0xf
31 #define RFE_DONT_CARE 0xff
32 #define PARA_IF 0x8
33 #define PARA_ELSE_IF 0x9
34 #define PARA_ELSE 0xa
35 #define PARA_END 0xb
36 #define PARA_CHK 0x4
47 u32 cut_para = 0, rfe_para = 0; in halbb_sel_headline()
48 u32 compare_target = 0; in halbb_sel_headline()
49 u32 cut_max = 0; in halbb_sel_headline()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x80000015, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]