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/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dvr1000.h14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
[all …]
H A Dbast.h16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)
17 #define BAST_CPLD_CTRL1_LRCADC (0x01)
18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)
19 #define BAST_CPLD_CTRL1_LRCARM (0x03)
20 #define BAST_CPLD_CTRL1_LRMASK (0x03)
24 #define BAST_CPLD_CTRL2_WNAND (0x04)
25 #define BAST_CPLD_CTLR2_IDERST (0x08)
29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)
30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)
34 #define BAST_CPLD_CTRL4_LLAT (0x01)
[all …]
/OK3568_Linux_fs/u-boot/arch/xtensa/dts/
H A Dxtfpga-flash-128m.dtsi7 reg = <0x00000000 0x08000000>;
10 partition@0x0 {
12 reg = <0x00000000 0x06000000>;
14 partition@0x6000000 {
16 reg = <0x06000000 0x00800000>;
18 partition@0x6800000 {
20 reg = <0x06800000 0x017e0000>;
22 partition@0x7fe0000 {
24 reg = <0x07fe0000 0x00020000>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dopenbmc-flash-layout-128.dtsi8 u-boot@0 {
9 reg = <0x0 0xe0000>; // 896KB
14 reg = <0xe0000 0x20000>; // 128KB
19 reg = <0x100000 0x900000>; // 9MB
24 reg = <0xa00000 0x5600000>; // 86MB
29 reg = <0x6000000 0x2000000>; // 32MB
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
H A Dstih410.dtsi16 usb2_picophy1: phy2@0 {
18 reg = <0 0>;
19 #phy-cells = <0>;
20 st,syscfg = <&syscfg_core 0xf8 0xf4>;
28 usb2_picophy2: phy3@0 {
30 reg = <0 0>;
31 #phy-cells = <0>;
32 st,syscfg = <&syscfg_core 0xfc 0xf4>;
42 reg = <0x9a03c00 0x100>;
57 reg = <0x9a03e00 0x100>;
[all …]
H A Domap3-ldp.dts17 reg = <0x80000000 0x8000000>; /* 128 MB */
21 cpu@0 {
29 pinctrl-0 = <&gpio_key_pins>;
97 ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */
98 <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */
100 nand@0,0 {
102 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
104 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
111 gpmc,sync-clk-ps = <0>;
112 gpmc,cs-on-ns = <0>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dst,st-hva.txt18 reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dcdns,usb3.yaml85 reg = <0x00 0x6000000 0x00 0x10000>,
86 <0x00 0x6010000 0x00 0x10000>,
87 <0x00 0x6020000 0x00 0x10000>;
H A Dti,j721e-usb.yaml38 If present, it restricts the controller to USB2.0 mode of
85 reg = <0x00 0x4104000 0x00 0x100>;
96 reg = <0x00 0x6000000 0x00 0x10000>,
97 <0x00 0x6010000 0x00 0x10000>,
98 <0x00 0x6020000 0x00 0x10000>;
100 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
102 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
/OK3568_Linux_fs/u-boot/include/configs/
H A Dsmdkv310.h25 #define CONFIG_SYS_SDRAM_BASE 0x40000000
26 #define CONFIG_SYS_TEXT_BASE 0x43E00000
29 #define S5P_CHECK_SLEEP 0x00000BAD
30 #define S5P_CHECK_DIDLE 0xBAD00000
31 #define S5P_CHECK_LPA 0xABAD0000
35 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
42 #define COPY_BL2_FNPTR_ADDR 0x00002488
44 #define CONFIG_SPL_TEXT_BASE 0x02021410
46 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
49 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
[all …]
H A Dorigen.h22 #define CONFIG_SYS_SDRAM_BASE 0x40000000
28 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
29 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
31 #define CONFIG_SYS_TEXT_BASE 0x43E00000
39 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
43 #define CONFIG_SYS_MONITOR_BASE 0x00000000
46 #define S5P_CHECK_SLEEP 0x00000BAD
47 #define S5P_CHECK_DIDLE 0xBAD00000
48 #define S5P_CHECK_LPA 0xABAD0000
53 #define COPY_BL2_FNPTR_ADDR 0x02020030
[all …]
/OK3568_Linux_fs/u-boot/cmd/fastboot/
H A DKconfig36 default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
37 default 0x81000000 if ARCH_OMAP2PLUS
38 default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
39 default 0x22000000 if ARCH_SUNXI && MACH_SUN9I
40 default 0x60800800 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \
42 default 0x800800 if ROCKCHIP_RK3288 || ROCKCHIP_RK3329 || \
44 default 0x280000 if ROCKCHIP_RK3368
45 default 0x100000 if ARCH_ZYNQMP
53 default 0x8000000 if ARCH_ROCKCHIP
54 default 0x6000000 if ARCH_ZYNQMP
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dstih410.dtsi18 cpu@0 {
19 st,syscfg = <&syscfg_core 0x8e0>;
20 st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
35 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
41 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
46 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
51 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
60 reg = <0x08a6583c 0x8>;
65 #phy-cells = <0>;
66 st,syscfg = <&syscfg_core 0xf8 0xf4>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ux500/
H A Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/pasemi/
H A Dsetup.c51 static int nmi_virq = 0;
61 out_le32(reset_reg, 0x6000000); in pas_restart()
68 void __iomem *pld_map = ioremap(0xf5000000,4096); in pas_shutdown()
70 out_8(pld_map+7,0x01); in pas_shutdown()
76 .start = 0x70,
77 .end = 0x71,
126 set_tb(timebase >> 32, timebase & 0xffffffff); in pas_take_timebase()
127 timebase = 0; in pas_take_timebase()
152 reset_reg = ioremap(0xfc101100, 4); in pas_setup_arch()
162 reg = 0; in pas_setup_mce_regs()
[all …]
/OK3568_Linux_fs/kernel/arch/sparc/include/asm/
H A Dpgtable_64.h26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
27 * The page copy blockops can use 0x6000000 to 0x8000000.
28 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range.
29 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range.
30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
31 * The vmalloc area spans 0x100000000 to 0x200000000.
33 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
34 * There is a single static kernel PMD which maps from 0x0 to address
35 * 0x400000000.
37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200-main.dtsi11 reg = <0x00 0x70000000 0x00 0x100000>;
14 ranges = <0x00 0x00 0x70000000 0x100000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
23 reg = <0x00 0x00100000 0x00 0x1c000>;
26 ranges = <0x00 0x00 0x00100000 0x1c000>;
31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]

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