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Searched +full:0 +full:x503c0100 (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/socionext/
H A Dsocionext,uniphier-system-cache.yaml70 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
71 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
73 cache-size = <0x140000>;
83 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
84 interrupts = <0 190 4>, <0 191 4>;
86 cache-size = <0x200000>;
95 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
96 interrupts = <0 174 4>, <0 175 4>;
98 cache-size = <0x200000>;
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/arm32/
H A Dcache-uniphier.c18 #define UNIPHIER_SSCC 0x500c0000 /* Control Register */
19 #define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
20 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
21 #define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
22 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
23 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
24 #define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
25 #define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
28 #define UNIPHIER_SSCID 0x503c0100 /* ID Register */
31 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Duniphier-sld8.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
71 #size-cells = <0>;
[all …]
H A Duniphier-ld4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
71 #size-cells = <0>;
[all …]
H A Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
79 #size-cells = <0>;
[all …]
H A Duniphier-pro5.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
[all …]
H A Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
162 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
163 <0x506c0000 0x400>;
164 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
175 reg = <0x54006000 0x100>;
177 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Duniphier-ld4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
59 interrupts = <0 174 4>, <0 175 4>;
70 reg = <0x54006800 0x40>;
71 interrupts = <0 33 4>;
[all …]
H A Duniphier-sld8.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
59 interrupts = <0 174 4>, <0 175 4>;
70 reg = <0x54006800 0x40>;
71 interrupts = <0 33 4>;
[all …]
H A Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
67 interrupts = <0 174 4>, <0 175 4>;
78 reg = <0x54006800 0x40>;
79 interrupts = <0 33 4>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
139 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
140 <0x506c0000 0x400>;
141 interrupts = <0 190 4>, <0 191 4>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
[all …]
H A Duniphier-pxs2.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
106 #clock-cells = <0>;
111 #clock-cells = <0>;
127 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
128 <0x506c0000 0x400>;
129 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
140 reg = <0x54006800 0x40>;
141 interrupts = <0 33 4>;
[all …]