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/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Domap54xx.h17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
[all …]
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
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H A Dam33xx.h19 #define L4_SLOW_AM33XX_BASE 0x48000000
21 #define AM33XX_SCM_BASE 0x44E10000
23 #define AM33XX_PRCM_BASE 0x44E00000
24 #define AM43XX_PRCM_BASE 0x44DF0000
25 #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC)
H A Dti81xx.h19 #define L4_SLOW_TI81XX_BASE 0x48000000
21 #define TI81XX_SCM_BASE 0x48140000
23 #define TI81XX_PRCM_BASE 0x48180000
27 * TI81XX register for checking device ID (it adds 0x204 to tap base while
28 * TI81XX DEVICE ID register is at offset 0x600 from control base).
31 TI81XX_CONTROL_DEVICE_ID - 0x204)
34 #define TI81XX_ARM_INTC_BASE 0x48200000
H A Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/omap/
H A Dl4.txt27 reg = <0x48000000 0x800>,
28 <0x48000800 0x800>,
29 <0x48001000 0x400>,
30 <0x48001400 0x400>,
31 <0x48001800 0x400>,
32 <0x48001c00 0x400>;
36 ranges = <0 0x48000000 0x100000>;
/OK3568_Linux_fs/u-boot/include/configs/
H A Drcar-gen3-common.h48 #define CONFIG_SYS_TEXT_BASE 0x50000000
49 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0)
51 #define DRAM_RSV_SIZE 0x08000000
54 #define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
55 #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
56 #define PHYS_SDRAM_2 0x500000000
57 #define PHYS_SDRAM_2_SIZE 0x40000000u
58 #define PHYS_SDRAM_3 0x600000000
59 #define PHYS_SDRAM_3_SIZE 0x40000000u
60 #define PHYS_SDRAM_4 0x700000000
[all …]
H A Dorigen.h22 #define CONFIG_SYS_SDRAM_BASE 0x40000000
28 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
29 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
31 #define CONFIG_SYS_TEXT_BASE 0x43E00000
39 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
43 #define CONFIG_SYS_MONITOR_BASE 0x00000000
46 #define S5P_CHECK_SLEEP 0x00000BAD
47 #define S5P_CHECK_DIDLE 0xBAD00000
48 #define S5P_CHECK_LPA 0xABAD0000
53 #define COPY_BL2_FNPTR_ADDR 0x02020030
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/OK3568_Linux_fs/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr25 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
26 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
27 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
30 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
31 0x14000000 - 0x17ffffff(CS5) | I2C | USB
32 0x18000000 - 0x1bffffff(CS6) | reserved | SD
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A D53c700_d.h_shipped28 ABSOLUTE Device_ID = 0 ; ID of target for command
29 ABSOLUTE MessageCount = 0 ; Number of bytes in message
30 ABSOLUTE MessageLocation = 0 ; Addr of message
31 ABSOLUTE CommandCount = 0 ; Number of bytes in command
32 ABSOLUTE CommandAddress = 0 ; Addr of Command
33 ABSOLUTE StatusAddress = 0 ; Addr to receive status return
34 ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
42 ABSOLUTE SGScriptStartAddress = 0
45 ; this: 0xPRS where
48 ABSOLUTE AFTER_SELECTION = 0x100
[all …]
/OK3568_Linux_fs/kernel/Documentation/arm/
H A Dixp4xx.rst78 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
87 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dox810se.dtsi17 #address-cells = <0>;
18 #size-cells = <0>;
29 /* Max 256MB @ 0x48000000 */
30 reg = <0x48000000 0x10000000>;
36 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
62 #clock-cells = <0>;
70 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a77961-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x78000000>;
25 reg = <0x4 0x80000000 0x0 0x80000000>;
30 reg = <0x6 0x00000000 0x1 0x00000000>;
H A Dr8a77950-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
H A Dr8a779a0-falcon-cpu.dtsi17 reg = <0x0 0x48000000 0x0 0x78000000>;
22 reg = <0x5 0x00000000 0x0 0x80000000>;
27 reg = <0x6 0x00000000 0x0 0x80000000>;
32 reg = <0x7 0x00000000 0x0 0x80000000>;
H A Dr8a77965-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x78000000>;
31 clock-names = "du.0", "du.1", "du.3",
32 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77960-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x6 0x00000000 0x0 0x40000000>;
36 clock-names = "du.0", "du.1", "du.2",
37 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774a1-hihope-rzg2m.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774e1-hihope-rzg2h.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x5 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774a1-hihope-rzg2m-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774b1-hihope-rzg2n-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774b1-hihope-rzg2n.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/
H A Ddma-controller.yaml26 reg = <0x48000000 0x1000>;
27 interrupts = <0 12 0x4
28 0 13 0x4
29 0 14 0x4
30 0 15 0x4>;
34 dma-channel-mask = <0xfffe>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dfaraday,ftintc010.txt22 reg = <0x48000000 0x1000>;
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/include/mach/
H A Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]

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