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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h13 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
14 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
15 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
16 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
17 #define DMA_BASE 0x31000000 /* DMA controller registers base */
18 #define USB_BASE 0x31020000 /* USB registers base */
19 #define LCD_BASE 0x31040000 /* LCD registers base */
20 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
21 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
24 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml102 reg = <0x5800a000 0x2000>;
116 st,syscon = <&syscfg 0x4>;
126 reg = <0x40028000 0x8000>;
128 interrupts = <0 61 0>, <0 62 0>;
131 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
132 st,syscon = <&syscfg 0x4>;
141 reg = <0x40028000 0x8000>;
147 st,syscon = <&syscfg 0x4>;
/OK3568_Linux_fs/kernel/arch/arm/include/debug/
H A Dvf.S6 #define VF_UART0_BASE_ADDR 0x40027000
7 #define VF_UART1_BASE_ADDR 0x40028000
8 #define VF_UART2_BASE_ADDR 0x40029000
9 #define VF_UART3_BASE_ADDR 0x4002a000
14 #define VF_UART_VIRTUAL_BASE 0xfe000000
18 and \rv, \rp, #0xffffff @ offset within 16MB section
23 strb \rd, [\rx, #0x7] @ Data Register
27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/
H A Dgpio_lpc32xx.txt9 0: GPIO P0
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
24 reg = <0x40028000 0x1000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dvf610-clock.txt29 reg = <0x4006b000 0x1000>;
37 reg = <0x40028000 0x1000>;
38 interrupts = <0 62 0x04>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dvf.dtsi38 reg = <0x40000000 0x00070000>;
43 reg = <0x40027000 0x1000>;
49 reg = <0x40028000 0x1000>;
55 reg = <0x40029000 0x1000>;
61 reg = <0x4002a000 0x1000>;
67 #size-cells = <0>;
69 reg = <0x4002c000 0x1000>;
76 #size-cells = <0>;
78 reg = <0x4002d000 0x1000>;
85 #size-cells = <0>;
[all …]
H A Dstm32f746.dtsi56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
78 reg = <0xA0000000 0x1000>;
79 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
86 #size-cells = <0>;
87 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
91 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
96 reg = <0x40011000 0x400>;
98 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 reg = <0x40000000 0x400>;
[all …]
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug138 0x80000000 | 0xf0000000 | UART0
139 0x80004000 | 0xf0004000 | UART1
140 0x80008000 | 0xf0008000 | UART2
141 0x8000c000 | 0xf000c000 | UART3
142 0x80010000 | 0xf0010000 | UART4
143 0x80014000 | 0xf0014000 | UART5
144 0x80018000 | 0xf0018000 | UART6
145 0x8001c000 | 0xf001c000 | UART7
146 0x80020000 | 0xf0020000 | UART8
147 0x80024000 | 0xf0024000 | UART9
[all …]