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12

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dclearstate_vi.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
H A Dclearstate_ci.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
H A Dclearstate_gfx9.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0x00000000, // DB_HTILE_DATA_BASE_HI
33 0x00000000, // DB_DEPTH_SIZE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
H A Dclearstate_si.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
H A Dclearstate_gfx10.h25 0x00000000, // DB_RENDER_CONTROL
26 0x00000000, // DB_COUNT_CONTROL
27 0x00000000, // DB_DEPTH_VIEW
28 0x00000000, // DB_RENDER_OVERRIDE
29 0x00000000, // DB_RENDER_OVERRIDE2
30 0x00000000, // DB_HTILE_DATA_BASE
31 0x00000000, // HOLE
32 0x00000000, // DB_DEPTH_SIZE_XY
33 0x00000000, // DB_DEPTH_BOUNDS_MIN
34 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dclearstate_ci.h28 0x00000000, // DB_RENDER_CONTROL
29 0x00000000, // DB_COUNT_CONTROL
30 0x00000000, // DB_DEPTH_VIEW
31 0x00000000, // DB_RENDER_OVERRIDE
32 0x00000000, // DB_RENDER_OVERRIDE2
33 0x00000000, // DB_HTILE_DATA_BASE
34 0, // HOLE
35 0, // HOLE
36 0x00000000, // DB_DEPTH_BOUNDS_MIN
37 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
H A Dclearstate_si.h28 0x00000000, // DB_RENDER_CONTROL
29 0x00000000, // DB_COUNT_CONTROL
30 0x00000000, // DB_DEPTH_VIEW
31 0x00000000, // DB_RENDER_OVERRIDE
32 0x00000000, // DB_RENDER_OVERRIDE2
33 0x00000000, // DB_HTILE_DATA_BASE
34 0, // HOLE
35 0, // HOLE
36 0x00000000, // DB_DEPTH_BOUNDS_MIN
37 0x00000000, // DB_DEPTH_BOUNDS_MAX
[all …]
H A Dclearstate_evergreen.h26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0, // HOLE
35 0, // HOLE
[all …]
H A Dclearstate_cayman.h28 0x00000000, // DB_RENDER_CONTROL
29 0x00000000, // DB_COUNT_CONTROL
30 0x00000000, // DB_DEPTH_VIEW
31 0x00000000, // DB_RENDER_OVERRIDE
32 0x00000000, // DB_RENDER_OVERRIDE2
33 0x00000000, // DB_HTILE_DATA_BASE
34 0, // HOLE
35 0, // HOLE
36 0, // HOLE
37 0, // HOLE
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Darm,mps2-uart.txt16 reg = <0x40004000 0x1000>;
17 interrupts = <0 1 12>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dst,stm32-spdifrx.yaml22 const: 0
68 #sound-dai-cells = <0>;
69 reg = <0x40004000 0x400>;
73 dmas = <&dmamux1 2 93 0x400 0x0>,
74 <&dmamux1 3 94 0x400 0x0>;
76 pinctrl-0 = <&spdifrx_pins>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h13 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
14 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
15 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
16 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
17 #define DMA_BASE 0x31000000 /* DMA controller registers base */
18 #define USB_BASE 0x31020000 /* USB registers base */
19 #define LCD_BASE 0x31040000 /* LCD registers base */
20 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
21 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
24 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
/OK3568_Linux_fs/u-boot/cmd/ddr_tool/stressapptest/
H A Dstressapptest.c40 0x00000001, 0x00000002, 0x00000004, 0x00000008,
41 0x00000010, 0x00000020, 0x00000040, 0x00000080,
42 0x00000100, 0x00000200, 0x00000400, 0x00000800,
43 0x00001000, 0x00002000, 0x00004000, 0x00008000,
44 0x00010000, 0x00020000, 0x00040000, 0x00080000,
45 0x00100000, 0x00200000, 0x00400000, 0x00800000,
46 0x01000000, 0x02000000, 0x04000000, 0x08000000,
47 0x10000000, 0x20000000, 0x40000000, 0x80000000,
48 0x40000000, 0x20000000, 0x10000000, 0x08000000,
49 0x04000000, 0x02000000, 0x01000000, 0x00800000,
[all …]
/OK3568_Linux_fs/kernel/arch/sparc/
H A DKconfig395 default 0x40004000
399 This address is normally the base address of main memory + 0x4000.
403 default 0x00080000
412 default 0xf0004000
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3528/
H A Drk3528.c16 #define FIREWALL_DDR_BASE 0xff2e0000
17 #define FW_DDR_MST1_REG 0x44
18 #define FW_DDR_MST6_REG 0x58
19 #define FW_DDR_MST7_REG 0x5c
20 #define FW_DDR_MST11_REG 0x6c
21 #define FW_DDR_MST14_REG 0x78
22 #define FW_DDR_MST16_REG 0x80
23 #define FW_DDR_MST_REG 0xf0
25 #define VENC_GRF_BASE 0xff320000
26 #define VENC_GRF_CON1 0x4
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen9_renderstate.c29 0x000007a8,
30 0x000007b4,
31 0x000007bc,
32 0x000007cc,
37 0x7a000004,
38 0x01000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
[all …]
H A Dgen8_renderstate.c29 0x00000798,
30 0x000007a4,
31 0x000007ac,
32 0x000007bc,
37 0x7a000004,
38 0x01000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dlpc18xx.dtsi19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \
24 } while (0)
27 #define PCIE_SNPS_DBI_BASE 0xf5000000
28 #define PCIE_SNPS_APB_BASE 0xfe150000
29 #define PCIE_SNPS_IATU_BASE 0xa40300000
31 #define PCI_RESBAR 0x2e8
33 #define PCIE_SNPS_DBI_BASE 0xf6000000
34 #define PCIE_SNPS_APB_BASE 0xfe280000
35 #define PCIE_SNPS_IATU_BASE 0x3c0b00000
37 #define PCI_RESBAR 0x2b8
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Drockchip-cpufreq.c60 int ret = 0; in px30_get_soc_info()
61 u8 value = 0; in px30_get_soc_info()
64 return 0; in px30_get_soc_info()
67 "performance") >= 0) { in px30_get_soc_info()
75 if (*bin >= 0) in px30_get_soc_info()
84 int ret = 0; in rk3288_get_soc_info()
85 u8 value = 0; in rk3288_get_soc_info()
90 if (of_property_match_string(np, "nvmem-cell-names", "special") >= 0) { in rk3288_get_soc_info()
96 if (value == 0xc) in rk3288_get_soc_info()
97 *bin = 0; in rk3288_get_soc_info()
[all …]
/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dsetup.c85 .start = 0,
86 .end = 0,
92 .start = 0,
93 .end = 0,
99 .start = 0,
100 .end = 0,
106 .start = 0,
107 .end = 0,
165 #define RAMDISK_IMAGE_START_MASK 0x07FF
166 #define RAMDISK_PROMPT_FLAG 0x8000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/phydm/txbf/
H A Dhaltxbf8822b.c15 #if 0
45 u4Byte TxRptData = 0;
46 u1Byte DataRate = 0xFF;
70 u1Byte Nr_index = 0;
80 if (idx == 0) {
82 case 0:
86 PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0x6); /*1ss*/
87 PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0x6); /*2ss*/
88 PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x10); /*BC*/
89 …PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0x6); /*set TxPath selection …
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip-mipi-csi-tx.c32 #define DSI_PHY_TMR_LPCLK_CFG 0x98
33 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
34 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
36 #define DSI_PHY_TMR_CFG 0x9c
37 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
38 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
39 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
41 #define DSI_PHY_RSTZ 0xa0
42 #define PHY_DISFORCEPLL 0
44 #define PHY_DISABLECLK 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/txbf/
H A Dhaltxbf8822b.c35 u8 ntx = 0; in hal_txbf_8822b_get_ntx()
39 if (*p_dm->hub_usb_mode == 2) {/*USB3.0*/ in hal_txbf_8822b_get_ntx()
71 u8 nrx = 0; in hal_txbf_8822b_get_nrx()
84 nrx = 0; in hal_txbf_8822b_get_nrx()
88 nrx = 0; in hal_txbf_8822b_get_nrx()
102 #if 0 in hal_txbf_8822b_rf_mode()
104 u8 i, nr_index = 0; in hal_txbf_8822b_rf_mode()
118 odm_set_rf_reg(p_dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1); in hal_txbf_8822b_rf_mode()
122 if ((p_beamforming_info->beamformee_su_cnt > 0) || (p_beamforming_info->beamformee_mu_cnt > 0)) { in hal_txbf_8822b_rf_mode()
124 odm_set_rf_reg(p_dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000); in hal_txbf_8822b_rf_mode()
[all …]

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