Searched +full:0 +full:x38100000 (Results 1 – 4 of 4) sorted by relevance
9 #define BSC1_BASE_ADDR 0x3e01600010 #define BSC2_BASE_ADDR 0x3e01700011 #define BSC3_BASE_ADDR 0x3e01800012 #define DWDMA_AHB_BASE_ADDR 0x3810000013 #define ESUB_CLK_BASE_ADDR 0x3800000014 #define ESW_CONTRL_BASE_ADDR 0x3820000015 #define GPIO2_BASE_ADDR 0x3500300016 #define HSOTG_BASE_ADDR 0x3f12000017 #define HSOTG_CTRL_BASE_ADDR 0x3f13000018 #define KONA_MST_CLK_BASE_ADDR 0x3f001000[all …]
46 "p2u-N": where N ranges from 0 to one less than the total number of lanes49 0: C064 - cell 0 specifies the bus and device numbers of the root port:67 - cell 1 denotes the upper 32 address bits and should be 080 - 0x81000000: I/O memory region81 - 0x82000000: non-prefetchable memory region82 - 0xc2000000: prefetchable memory region103 - pinctrl-0: phandle for the 'default' state of pin configuration.146 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */147 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */[all …]
55 "^dwc3@[0-9a-f]+$":80 reg = <0x32f10100 0x8>;87 dma-ranges = <0x40000000 0x40000000 0xc0000000>;92 reg = <0x38100000 0x10000>;
46 #clock-cells = <0>;53 #clock-cells = <0>;60 #clock-cells = <0>;67 #clock-cells = <0>;74 #clock-cells = <0>;81 #clock-cells = <0>;88 #clock-cells = <0>;95 #size-cells = <0>;97 A53_0: cpu@0 {100 reg = <0x0>;[all …]