Searched +full:0 +full:x310d0000 (Results 1 – 4 of 4) sorted by relevance
45 pattern: "^cpts@[0-9a-f]+$"93 const: 0124 reg = <0x310d0000 0x400>;128 interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;134 #clock-cells = <0>;
11 reg = <0x00 0x70000000 0x00 0x100000>;14 ranges = <0x00 0x00 0x70000000 0x100000>;16 atf-sram@0 {17 reg = <0x00 0x20000>;23 reg = <0x00 0x00100000 0x00 0x1c000>;26 ranges = <0x00 0x00 0x00100000 0x1c000>;31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */[all …]
12 reg = <0x0 0x70000000 0x0 0x200000>;15 ranges = <0x0 0x0 0x70000000 0x200000>;17 atf-sram@0 {18 reg = <0x0 0x20000>;22 reg = <0xf0000 0x10000>;26 reg = <0x100000 0x100000>;37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */38 <0x00 0x01880000 0x00 0x90000>, /* GICR */39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;19 #clock-cells = <0>;21 clock-frequency = <0>;28 reg = <0x0 0x70000000 0x0 0x800000>;31 ranges = <0x0 0x0 0x70000000 0x800000>;33 atf-sram@0 {34 reg = <0x0 0x20000>;40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */43 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]