Home
last modified time | relevance | path

Searched +full:0 +full:x3000 (Results 1 – 25 of 1008) sorted by relevance

12345678910>>...41

/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6ul-ccimx6ulsom.dtsi12 reg = <0x80000000 0>; /* will be filled by U-Boot */
23 size = <0x4000000>;
35 pinctrl-0 = <&pinctrl_gpmi_nand>;
42 pinctrl-0 = <&pinctrl_i2c1>;
47 reg = <0x08>;
172 pinctrl-0 = <&pinctrl_uart1>;
180 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>;
191 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
192 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
193 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
[all …]
H A Datlas7.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
60 interrupts = <0 29 4>, <0 82 4>;
67 ranges = <0x10000000 0x10000000 0xc0000000>;
73 reg = <0x10301000 0x1000>,
74 <0x10302000 0x0100>;
79 reg = <0x10E30020 0x4>;
[all …]
H A Dimx6ul-ccimx6ulsbcpro.dts21 pwms = <&pwm5 0 50000>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
51 pinctrl-0 = <&pinctrl_adc1>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1_master>;
79 pinctrl-0 = <&pinctrl_enet1>;
87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
96 #size-cells = <0>;
98 ethphy0: ethernet-phy@0 {
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/
H A Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
H A Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/rtl8822b/pci/
H A Drtl8822be_halinit.c47 0x3000)); in InitMAC_TRXBD_8822BE()
113 if (((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32 != 0) { in InitMAC_TRXBD_8822BE()
119 RTW_INFO("MGNT_QUEUE HA=0\n"); in InitMAC_TRXBD_8822BE()
126 /* pci buffer descriptor mode: Reset the Read/Write point to 0 */ in InitMAC_TRXBD_8822BE()
127 PlatformEFIOWrite4Byte(Adapter, REG_TSFTIMER_HCI_8822B, 0x3fffffff); in InitMAC_TRXBD_8822BE()
129 /* Reset the H2CQ R/W point index to 0 */ in InitMAC_TRXBD_8822BE()
134 rtw_write8(Adapter, REG_PCIE_CTRL + 3, (tmpU1b | 0xF7)); in InitMAC_TRXBD_8822BE()
138 rtw_write32(Adapter, REG_INT_MIG, 0); in InitMAC_TRXBD_8822BE()
142 rtw_write32(Adapter, REG_MCUTST_I_8822B, 0x0); in InitMAC_TRXBD_8822BE()
146 rtw_write32(Adapter, REG_MACID, 0x87654321); in InitMAC_TRXBD_8822BE()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dmpc8548cds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x01000000>;
44 partition@0 {
45 reg = <0x0 0x0b00000>;
50 reg = <0x0b00000 0x0400000>;
55 reg = <0x0f00000 0x060000>;
60 reg = <0x0f60000 0x020000>;
66 reg = <0x0f80000 0x080000>;
72 board-control@1,0 {
74 reg = <0x1 0x0 0x1000>;
[all …]
H A Dpq3-i2c-0.dtsi2 * PQ3 I2C device tree stub [ controller @ offset 0x3000 ]
37 #size-cells = <0>;
38 cell-index = <0>;
40 reg = <0x3000 0x100>;
41 interrupts = <43 2 0 0>;
/OK3568_Linux_fs/kernel/sound/isa/msnd/
H A Dmsnd.c48 writew(0, base + JQS_wHead); in snd_msnd_init_queue()
49 writew(0, base + JQS_wTail); in snd_msnd_init_queue()
58 while (timeout-- > 0) in snd_msnd_wait_TXDE()
60 return 0; in snd_msnd_wait_TXDE()
70 while (timeout-- > 0) in snd_msnd_wait_HC0()
72 return 0; in snd_msnd_wait_HC0()
82 if (snd_msnd_wait_HC0(dev) == 0) { in snd_msnd_send_dsp_cmd()
85 return 0; in snd_msnd_send_dsp_cmd()
100 if (snd_msnd_wait_TXDE(dev) == 0) { in snd_msnd_send_word()
104 return 0; in snd_msnd_send_word()
[all …]
/OK3568_Linux_fs/buildroot/board/freescale/common/imx/
H A Dimx8-bootloader-prepare.sh13 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00910000 ${HOS…
14 ${HOST_DIR}/bin/mkimage -E -p 0x3000 -f ${BINARIES_DIR}/u-boot.its ${BINARIES_DIR}/u-boot.itb
17 …n -loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x7E1000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x…
20 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00920000 ${HOS…
21 ${HOST_DIR}/bin/mkimage -E -p 0x3000 -f ${BINARIES_DIR}/u-boot.its ${BINARIES_DIR}/u-boot.itb
24 …t -loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x7E1000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x…
27 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00960000 ${HOS…
28 ${HOST_DIR}/bin/mkimage -E -p 0x3000 -f ${BINARIES_DIR}/u-boot.its ${BINARIES_DIR}/u-boot.itb
31 …t -loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x912000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x…
34 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00970000 ${HOS…
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/OK3568_Linux_fs/kernel/drivers/net/dsa/mv88e6xxx/
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
H A Dglobal1.h16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
33 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
/OK3568_Linux_fs/kernel/arch/alpha/kernel/
H A Dbinfmt_loader.c16 if (eh->fh.f_magic != 0x183 || (eh->fh.f_flags & 0x3000) != 0x3000) in load_binary()
30 bprm->taso = eh->ah.entry < 0x100000000UL; in load_binary()
34 return 0; in load_binary()
44 return 0; in init_loader_binfmt()
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dkdump.h7 #define KDUMP_KERNELBASE 0x2000000
12 #define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
23 #define KDUMP_TRAMPOLINE_START 0x0100
24 #define KDUMP_TRAMPOLINE_END 0x3000
26 #define KDUMP_TRAMPOLINE_START (0x0100 + PAGE_OFFSET)
27 #define KDUMP_TRAMPOLINE_END (0x3000 + PAGE_OFFSET)
/OK3568_Linux_fs/kernel/arch/arm/mach-ux500/
H A Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/atomisp/i2c/
H A Dov2722.h38 #define I2C_MSG_LENGTH 0x2
50 * bits 31-16: numerator, bits 15-0: denominator
52 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
56 * bits 31-16: numerator, bits 15-0: denominator
58 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
65 * bits 7-0: min f-number denominator
67 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
68 #define OV2720_ID 0x2720
69 #define OV2722_ID 0x2722
71 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boot/romimage/
H A Dmmcif-sh7724.c14 #define MMCIF_BASE (void __iomem *)0xa4ca0000
16 #define MSTPCR2 0xa4150038
17 #define PTWCR 0xa4050146
18 #define PTXCR 0xa4050148
19 #define PSELA 0xa405014e
20 #define PSELE 0xa4050156
21 #define HIZCRC 0xa405015c
22 #define DRVCRA 0xa405018a
42 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
45 __raw_writew(0x0000, PTWCR); in mmcif_loader()
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/type_traits/detail/
H A Dconfig.hpp29 # if (BOOST_WORKAROUND(__MWERKS__, < 0x3000) \
31 || BOOST_WORKAROUND(__BORLANDC__, < 0x5A0) \
34 || BOOST_WORKAROUND(MPW_CPLUS, BOOST_TESTED_AT(0x890)) \
35 || BOOST_WORKAROUND(__SUNPRO_CC, BOOST_TESTED_AT(0x580))) \
60 #if BOOST_WORKAROUND(__MWERKS__, < 0x3000) || BOOST_WORKAROUND(__IBMCPP__, <= 600)
/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-snps-pcie3.fw1 0x081D,
2 0xFFFF,
3 0x33AF,
4 0x33AE,
5 0x0C4F,
6 0xD10D,
7 0x0D0F,
8 0xD306,
9 0x0C8F,
10 0xDB06,
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.fw1 0x081D,
2 0xFFFF,
3 0x33AF,
4 0x33AE,
5 0x0C4F,
6 0xD10D,
7 0x0D0F,
8 0xD306,
9 0x0C8F,
10 0xDB06,
[all …]

12345678910>>...41