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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-pinctrl.h20 mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */
24 mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
25 mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
26 mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
27 mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
28 mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
29 mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
30 mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
31 mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
32 mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h30 u32 ccr; /* 0x0000 */
34 u32 cacrr; /* 0x0010*/
38 u32 cscmr2; /* 0x0020 */
42 u32 cdcdr; /* 0x0030 */
46 u32 cscdr4; /* 0x0040 */
50 u32 ctor; /* 0x0050 */
54 u32 ccosr; /* 0x0060 */
58 u32 CCGR2; /* 0x0070 */
62 u32 CCGR6; /* 0x0080 */
64 u32 CCGR7; /* 0x0084 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx35/
H A Dcrm_regs.h16 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
20 #define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
22 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
29 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
31 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
34 #define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
36 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
37 #define MXC_CCM_PDR0_AUTO_CON 0x1
40 #define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/berlin/
H A Dberlin-bg4ct.c18 BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
19 BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */
20 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */
21 BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
22 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
23 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */
24 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */
25 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
26 BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
27 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
[all …]
H A Dpinctrl-as370.c18 BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
19 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO0 */
20 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKIO */
21 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG0 */
22 BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
23 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO1 */
24 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKIO */
25 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG1 */
26 BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
27 BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 1P8V RSTB*/
[all …]
H A Dberlin-bg2q.c19 BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
20 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
21 BERLIN_PINCTRL_FUNCTION(0x1, "mmc"),
22 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
23 BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
24 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
25 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
26 BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
27 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
28 BERLIN_PINCTRL_FUNCTION(0x2, "arc"),
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx7ulp-pinfunc.h26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
[all …]
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
24 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
25 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h17 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
18 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
19 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
20 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
21 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
22 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
23 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
24 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
25 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
26 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h118 #define CCM_CCR_OSCNT_MASK 0xff
119 #define CCM_CCR_OSCNT(v) ((v) & 0xff)
122 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
123 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
126 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
127 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
141 #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
142 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
143 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
146 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/x86/crypto/
H A Dserpent-avx2-asm_64.S21 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
26 .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
31 .byte 0x0e, 1, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0
61 #define S0_1(x0, x1, x2, x3, x4) \ argument
62 vpor x0, x3, tp; \
63 vpxor x3, x0, x0; \
64 vpxor x2, x3, x4; \
66 vpxor x1, tp, x3; \
70 #define S0_2(x0, x1, x2, x3, x4) \ argument
71 vpxor x3, x0, x0; \
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/sunxi/
H A Dpinctrl-sun4i-a10.c22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
28 SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h11 #define IOMUXC_GPR0 0x00
12 #define IOMUXC_GPR1 0x04
13 #define IOMUXC_GPR2 0x08
14 #define IOMUXC_GPR3 0x0c
15 #define IOMUXC_GPR4 0x10
16 #define IOMUXC_GPR5 0x14
17 #define IOMUXC_GPR6 0x18
18 #define IOMUXC_GPR7 0x1c
19 #define IOMUXC_GPR8 0x20
20 #define IOMUXC_GPR9 0x24
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h15 unsigned char res1[0x10];
28 unsigned char res2[0x4];
69 unsigned char res3[0x288];
72 unsigned char res4[0x10];
79 unsigned char res5[0xc];
82 unsigned char res6[0x2c];
88 unsigned char res7[0x8];
91 unsigned char res8[0x1c];
93 unsigned char res9[0x200];
99 unsigned char res10[0x2c];
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-of-pxa1928.c26 #define MPMU_UART_PLL 0x14
37 {0, "clk32", NULL, 0, 32768},
38 {0, "vctcxo", NULL, 0, 26000000},
39 {0, "pll1_624", NULL, 0, 624000000},
40 {0, "pll5p", NULL, 0, 832000000},
41 {0, "pll5", NULL, 0, 1248000000},
42 {0, "usb_pll", NULL, 0, 480000000},
46 {0, "pll1_d2", "pll1_624", 1, 2, 0},
47 {0, "pll1_d9", "pll1_624", 1, 9, 0},
48 {0, "pll1_d12", "pll1_624", 1, 12, 0},
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
42 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
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