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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-mt8192.yaml129 reg = <0x10005000 0x1000>,
130 <0x11c20000 0x1000>,
131 <0x11d10000 0x1000>,
132 <0x11d30000 0x1000>,
133 <0x11d40000 0x1000>,
134 <0x11e20000 0x1000>,
135 <0x11e70000 0x1000>,
136 <0x11ea0000 0x1000>,
137 <0x11f20000 0x1000>,
138 <0x11f30000 0x1000>,
[all …]
H A Dpinctrl-mt8183.txt53 Valid arguments are from 0 to 3.
57 are from 0 to 15.
60 are from 0 to 63.
75 driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
78 When E1=0/E0=0, the strength is 0.125mA.
79 When E1=0/E0=1, the strength is 0.25mA.
80 When E1=1/E0=0, the strength is 0.5mA.
82 So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
92 reg = <0 0x10005000 0 0x1000>,
93 <0 0x11f20000 0 0x1000>,
[all …]
H A Dmediatek,mt6779-pinctrl.yaml74 '-[0-9]*$':
115 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
116 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
117 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
120 enum: [0, 1, 2, 3]
126 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
127 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
128 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
131 enum: [0, 1, 2, 3]
152 reg = <0 0x10005000 0 0x1000>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi38 #size-cells = <0>;
72 cpu0: cpu@0 {
75 reg = <0x000>;
86 reg = <0x001>;
97 reg = <0x002>;
108 reg = <0x003>;
119 reg = <0x100>;
130 reg = <0x101>;
141 reg = <0x102>;
152 reg = <0x103>;
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
H A Dpinctrl-mt6779.c13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
H A Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]