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Searched +full:0 +full:x104000 (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dsh73a0.h5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/perf/
H A Darm,cmn.yaml52 reg = <0x50000000 0x4000000>;
53 /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
55 arm,root-node = <0x104000>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgf100.c34 nvkm_wr32(device, ce->addr + 0x084, index); in gf100_ce_init()
71 0x104000, pengine); in gf100_ce_new()
75 0x105000, pengine); in gf100_ce_new()
H A Dgt215.c36 { 0x0001, "ILLEGAL_MTHD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "INVALID_BITFIELD" },
47 const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000; in gt215_ce_intr()
48 u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; in gt215_ce_intr()
49 u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; in gt215_ce_intr()
50 u32 mthd = (addr & 0x07ff) << 2; in gt215_ce_intr()
51 u32 subc = (addr & 0x3800) >> 11; in gt215_ce_intr()
52 u32 data = nvkm_rd32(device, 0x104044 + base); in gt215_ce_intr()
59 chan ? chan->inst->addr : 0, in gt215_ce_intr()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
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H A Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.vxworks31 void (*kernel_entry)(fdt_addr, 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0)
49 value for "bootaddr" is 0x101200.
77 location at 0x4000 for "e820data" and 0x4a00 for "e820info". Typical values
78 for "e820data" and "e820info" are 0x104000 and 0x104a00. But there is one
/OK3568_Linux_fs/kernel/sound/pci/mixart/
H A Dmixart_hwdep.h31 #define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x))
36 #define DAUGHTER_TYPE_MASK 0x0F
37 #define DAUGHTER_VER_MASK 0xF0
40 #define MIXART_DAUGHTER_TYPE_NONE 0x00
41 #define MIXART_DAUGHTER_TYPE_COBRANET 0x08
42 #define MIXART_DAUGHTER_TYPE_AES 0x0E
50 …* -----------BAR 0 -------------------------------------------------------------------------------…
52 #define MIXART_PSEUDOREG 0x2000 /* base address for ps…
54 #define MIXART_PSEUDOREG_BOARDNUMBER MIXART_PSEUDOREG+0 /* board number */
57 #define MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET MIXART_PSEUDOREG+0x70 /* streaming load */
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/OK3568_Linux_fs/kernel/sound/pci/ctxfi/
H A Dct20k1reg.h10 #define DSPXRAM_START 0x000000
11 #define DSPXRAM_END 0x013FFC
12 #define DSPAXRAM_START 0x020000
13 #define DSPAXRAM_END 0x023FFC
14 #define DSPYRAM_START 0x040000
15 #define DSPYRAM_END 0x04FFFC
16 #define DSPAYRAM_START 0x020000
17 #define DSPAYRAM_END 0x063FFC
18 #define DSPMICRO_START 0x080000
19 #define DSPMICRO_END 0x0B3FFC
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/OK3568_Linux_fs/external/dpdk/pcie/e1000/
H A Digb_rxtx.c46 #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
62 #define IGB_TX_IEEE1588_TMST 0
98 IGB_RXQ_FLAG_LB_BSWAP_VLAN = 0x01,
123 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
124 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
134 IGB_CTX_0 = 0, /**< CTX0 */
157 #define TX_MACIP_LEN_CMP_MASK 0x000000000000FFFFULL /**< L2L3 header mask. */
158 #define TX_VLAN_CMP_MASK 0x00000000FFFF0000ULL /**< Vlan mask. */
159 #define TX_TCP_LEN_CMP_MASK 0x000000FF00000000ULL /**< TCP header mask. */
160 #define TX_TSO_MSS_CMP_MASK 0x00FFFF0000000000ULL /**< TSO segsz mask. */
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H A Digb_ethdev.c52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
69 #define E1000_VET_VET_EXT 0xFFFF0000
73 #define IGB_MSIX_OTHER_INTR_VEC 0
249 #define IGB_FC_PAUSE_TIME 0x0680
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
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H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
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