Searched +full:0 +full:x101c0000 (Results 1 – 19 of 19) sorted by relevance
8 cpu@0 {14 #address-cells = <0>;22 reg = <0x10000000 0x200000>;23 ranges = <0x0 0x10000000 0x1FFFFF>;28 sysc@0 {30 reg = <0x0 0x100>;35 reg = <0x200 0x100>;46 reg = <0x300 0x100>;51 reg = <0xc00 0x100>;62 reg = <0x101c0000 40000>;
10 #size-cells = <0>;12 cpu@0 {15 reg = <0>;25 #address-cells = <0>;33 reg = <0x10000000 0x200000>;34 ranges = <0x0 0x10000000 0x1FFFFF>;39 sysc: system-controller@0 {41 reg = <0x0 0x60>;46 reg = <0x60 0x8>;48 #size-cells = <0>;[all …]
52 reg = <0x101c0000 40000>;
43 0: Global Timer Interrupt 047 4: Local Timer Interrupt 078 reg = <0x10050000 0x800>;98 reg = <0x101C0000 0x800>;119 reg = <0x10050000 0x800>;139 reg = <0x10050000 0x800>;
42 <7 0>,60 reg = <0x02020000 0x54000>;63 ranges = <0 0x02020000 0x54000>;65 smp-sram@0 {67 reg = <0x0 0x1000>;72 reg = <0x53000 0x1000>;78 reg = <0x101c0000 0xb00>;95 reg = <0x101d0000 0x100>;101 reg = <0x12d10000 0x100>;111 reg = <0x12ca0000 0x1000>;[all …]
43 reg = <0x20018000 0x4000>;44 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,55 reg = <0x2001c000 0x4000>;56 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,68 reg = <0x20078000 0x4000>;82 #clock-cells = <0>;88 reg = <0x10090000 0x10000>;99 reg = <0x10138000 0x1000>;106 reg = <0x1013c000 0x100>;111 reg = <0x1013c200 0x20>;[all …]
38 #size-cells = <0>;44 reg = <0xf00>;53 reg = <0xf01>;99 reg = <0x20078000 0x4000>;100 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,141 #clock-cells = <0>;146 reg = <0x10080000 0x2000>;149 ranges = <0 0x10080000 0x2000>;151 smp-sram@0 {153 reg = <0x00 0x10>;[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0>;169 reg = <0x02020000 0x30000>;172 ranges = <0 0x02020000 0x30000>;174 smp-sram@0 {176 reg = <0x0 0x1000>;181 reg = <0x2f000 0x1000>;187 reg = <0x10044000 0x20>;188 #power-domain-cells = <0>;[all …]
75 #size-cells = <0>;80 reg = <0xf00>;89 reg = <0xf01>;95 reg = <0xf02>;101 reg = <0xf03>;112 14 254 0116 1 13 0190 reg = <0x20078000 0x4000>;191 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,231 vop-dclk-mode = <0>;[all …]
13 #define RT3883_SDRAM_BASE 0x0000000014 #define RT3883_SYSC_BASE 0x1000000015 #define RT3883_TIMER_BASE 0x1000010016 #define RT3883_INTC_BASE 0x1000020017 #define RT3883_MEMC_BASE 0x1000030018 #define RT3883_UART0_BASE 0x1000050019 #define RT3883_PIO_BASE 0x1000060020 #define RT3883_FSCC_BASE 0x1000070021 #define RT3883_NANDC_BASE 0x1000081022 #define RT3883_I2C_BASE 0x10000900[all …]
41 reg = <0x20018000 0x4000>;42 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,52 reg = <0x2001c000 0x4000>;53 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,64 reg = <0x20078000 0x4000>;77 #clock-cells = <0>;83 reg = <0x10138000 0x1000>;90 reg = <0x1013c000 0x100>;95 reg = <0x1013c200 0x20>;96 interrupts = <GIC_PPI 11 0x304>;[all …]
31 reg = <0x60000000 0x40000000>;43 #size-cells = <0>;49 reg = <0xf00>;62 reg = <0xf01>;75 reg = <0x20078000 0x4000>;77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,89 #clock-cells = <0>;109 reg = <0x20000000 0x1000>;119 reg = <0x0 0x20004000 0x0 0x1000>;124 reg = <0x20060000 0x100>;[all …]
41 reg = <0x60000000 0x40000000>;54 #size-cells = <0>;57 cpu0:cpu@0x000 {60 reg = <0x000>;70 cpu1:cpu@0x001 {73 reg = <0x001>;76 cpu2:cpu@0x002 {79 reg = <0x002>;82 cpu3:cpu@0x003 {85 reg = <0x003>;[all …]
48 #clock-cells = <0>;53 #size-cells = <0>;59 reg = <0x100>;71 reg = <0x101>;81 reg = <0x102>;91 reg = <0x103>;97 cpu4: cpu@0 {101 reg = <0x0>;113 reg = <0x1>;123 reg = <0x2>;[all …]