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Searched +full:0 +full:x10080000 (Results 1 – 23 of 23) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A DKconfig29 default 0xff0e1000
200 default 0xff704000
206 default 0xff718000
236 default 0xfff81000
242 default 0xfff84000
273 default 0xff091000
279 default 0xff098000
318 default 0xff8c1000
324 default 0xff8cffff
374 default 0xff8c2000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sram/
H A Dsram.yaml143 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
147 ranges = <0 0x5c000000 0x40000>;
150 reg = <0x100 0x50>;
154 reg = <0x1000 0x1000>;
159 reg = <0x20000 0x20000>;
174 reg = <0x02020000 0x54000>;
177 ranges = <0 0x02020000 0x54000>;
179 smp-sram@0 {
181 reg = <0x0 0x1000>;
186 reg = <0x53000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dlsi,axm5516-clks.txt18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dlpc4350.dtsi18 cpu@0 {
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Dlpc4357.dtsi18 cpu@0 {
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
H A Drk3188.dtsi25 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x0>;
42 reg = <0x1>;
50 reg = <0x2>;
58 reg = <0x3>;
111 reg = <0x10080000 0x8000>;
114 ranges = <0 0x10080000 0x8000>;
116 smp-sram@0 {
118 reg = <0x0 0x50>;
[all …]
H A Drk3066a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
34 reg = <0x0>;
42 reg = <0x1>;
84 reg = <0x10080000 0x10000>;
87 ranges = <0 0x10080000 0x10000>;
89 smp-sram@0 {
91 reg = <0x0 0x50>;
98 reg = <0x10091000 0x200>,
99 <0x10090000 0x100>,
[all …]
H A Drv1108.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
85 #clock-cells = <0>;
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
108 reg = <0x10080000 0x2000>;
111 ranges = <0 0x10080000 0x2000>;
116 reg = <0x10210000 0x100>;
125 pinctrl-0 = <&uart2m0_xfer>;
131 reg = <0x10220000 0x100>;
[all …]
H A Drk3036.dtsi38 #size-cells = <0>;
44 reg = <0xf00>;
53 reg = <0xf01>;
99 reg = <0x20078000 0x4000>;
100 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
141 #clock-cells = <0>;
146 reg = <0x10080000 0x2000>;
149 ranges = <0 0x10080000 0x2000>;
151 smp-sram@0 {
153 reg = <0x00 0x10>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
44 reg = <0x1>;
50 reg = <0x2>;
56 reg = <0x3>;
62 reg = <0x10080000 0x8000>;
65 ranges = <0 0x10080000 0x8000>;
67 smp-sram@0 {
69 reg = <0x0 0x50>;
[all …]
H A Drk3066a.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
43 reg = <0x1>;
49 reg = <0x10080000 0x10000>;
52 ranges = <0 0x10080000 0x10000>;
54 smp-sram@0 {
56 reg = <0x0 0x50>;
62 reg = <0x10118000 0x2000>;
65 #size-cells = <0>;
[all …]
H A Drv1108.dtsi32 #size-cells = <0>;
37 reg = <0xf00>;
63 mipi_dphy: mipi-dphy@0x20228000 {
65 reg = <0x20228000 0x8000>;
67 #clock-cells = <0>;
70 #phy-cells = <0>;
76 reg = <0x300e0000 0x10000>;
86 #size-cells = <0>;
88 pinctrl-0 = <&lcdc_mipi_data>;
93 #size-cells = <0>;
[all …]
H A Drk322x.dtsi30 #size-cells = <0>;
35 reg = <0xf00>;
49 reg = <0xf01>;
56 reg = <0xf02>;
63 reg = <0xf03>;
76 reg = <0x110f0000 0x4000>;
77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
96 reg = <0x60000000 0x40000000>;
118 #clock-cells = <0>;
123 reg = <0x10080000 0x9000>;
[all …]
H A Drk3036.dtsi31 reg = <0x60000000 0x40000000>;
43 #size-cells = <0>;
49 reg = <0xf00>;
62 reg = <0xf01>;
75 reg = <0x20078000 0x4000>;
77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89 #clock-cells = <0>;
109 reg = <0x20000000 0x1000>;
119 reg = <0x0 0x20004000 0x0 0x1000>;
124 reg = <0x20060000 0x100>;
[all …]
H A D.rv1108-evb.dtb.dts.tmp
H A D.rk3066a-mk808.dtb.dts.tmp
H A D.rk3188-radxarock.dtb.dts.tmp
H A D.rk3036-sdk.dtb.dts.tmp
/OK3568_Linux_fs/kernel/arch/m68k/coldfire/
H A Dm53xx.c30 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
31 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
32 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
33 DEFINE_CLK(0, "edma", 17, MCF_CLK);
34 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
35 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
36 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
37 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
38 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
39 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/loongson/
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
15 reg = <0 0x10000000 0 0x400>;
18 loongson,pic-base-vec = <0>;
24 reg = <0 0x10080000 0 0x100>;
34 reg = <0 0x10080100 0 0x100>;
44 reg = <0 0x10080200 0 0x100>;
54 reg = <0 0x10080300 0 0x100>;
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h31 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
38 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
47 #define MSR_LE (1<<0) /* Little Endian */
62 #define FPSCR_FX 0x80000000 /* FPU exception summary */
63 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
64 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
65 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
66 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
68 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dreg.h50 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
55 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
62 #define MSR_LE_LG 0 /* Little Endian */
77 #define MSR_SF 0
78 #define MSR_ISF 0
79 #define MSR_HV 0
80 #define MSR_S 0
88 #define MSR_SPE 0
102 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
107 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
[all …]