Searched +full:0 +full:x10014000 (Results 1 – 7 of 7) sorted by relevance
47 reg = <0x10014000 0x1000>;
31 #define CONFIG_SPL_TEXT_BASE 0xA000000035 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80037 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x80061 #define PHYS_SDRAM_1 0xA000000062 #define PHYS_SDRAM_2 0xB000000065 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */66 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */69 + PHYS_SDRAM_1_SIZE - 0x0100000)71 #define CONFIG_SYS_TEXT_BASE 0xA000080076 #define ACFG_MONITOR_OFFSET 0x00000000[all …]
43 /* 128 MiB memory @ 0x0 */44 reg = <0x00000000 0x08000000>;48 vmmc: fixedregulator@0 {57 #clock-cells = <0>;63 #clock-cells = <0>;71 #clock-cells = <0>;79 #clock-cells = <0>;87 #clock-cells = <0>;95 #clock-cells = <0>;103 #clock-cells = <0>;[all …]
44 /* 128 MiB memory @ 0x0 */45 reg = <0x00000000 0x08000000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;86 #clock-cells = <0>;94 #clock-cells = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;118 #clock-cells = <0>;[all …]
45 /* 128 MiB memory @ 0x0 */46 reg = <0x00000000 0x08000000>;67 #clock-cells = <0>;73 #clock-cells = <0>;81 #clock-cells = <0>;89 #clock-cells = <0>;97 #clock-cells = <0>;105 #clock-cells = <0>;113 pclk: pclk@0 {114 #clock-cells = <0>;[all …]
47 reg = <0x10040000 0x1000>;53 #clock-cells = <0>;59 #size-cells = <0>;62 cpu: cpu@0 {64 reg = <0>;88 reg = <0x10000000 0x20000>;93 reg = <0x10001000 0x1000>;104 reg = <0x10002000 0x1000>;111 reg = <0x10003000 0x1000>;120 reg = <0x10004000 0x1000>;[all …]
45 * The PB11MPCore has 512 MiB memory @ 0x7000000046 * and the first 256 are also remapped @ 0x0000000048 reg = <0x70000000 0x20000000>;53 #size-cells = <0>;56 MP11_0: cpu@0 {59 reg = <0>;91 reg = <0x1f001000 0x1000>,92 <0x1f000100 0x100>;97 reg = <0x1f002000 0x1000>;99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,[all …]