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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h16 #define CCM_GPR0_OFFSET 0x0
17 #define CCM_OBSERVE0_OFFSET 0x0400
18 #define CCM_SCTRL0_OFFSET 0x0800
19 #define CCM_CCGR0_OFFSET 0x4000
20 #define CCM_ROOT0_TARGET_OFFSET 0x8000
59 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
61 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
66 uint32_t ctrl_24m; /* offset 0x0000 */
70 uint32_t rcosc_config0; /* offset 0x0010 */
74 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/maps/
H A Dscx200_docflash.c27 static int probe = 0; /* Don't autoprobe */
28 static unsigned size = 0x1000000; /* 16 MiB the whole ISA address space */
32 module_param(probe, int, 0);
34 module_param(size, int, 0);
36 module_param(width, int, 0);
38 module_param(flashtype, charp, 0);
51 .offset = 0,
52 .size = 0xc0000
56 .offset = 0xc0000,
57 .size = 0x40000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h11 unsigned int pid; /* 0x00 */
12 unsigned char rsvd0[224]; /* 0x04 */
13 unsigned int rstype; /* 0xe4 */
14 unsigned char rsvd1[24]; /* 0xe8 */
15 unsigned int pllctl; /* 0x100 */
16 unsigned char rsvd2[4]; /* 0x104 */
17 unsigned int secctl; /* 0x108 */
18 unsigned int rv; /* 0x10c */
19 unsigned int pllm; /* 0x110 */
20 unsigned int prediv; /* 0x114 */
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boards/mach-microdev/
H A Dsetup.c21 [0] = {
22 .start = 0x300,
23 .end = 0x300 + SZ_4K - 1,
41 { S1DREG_MISC, 0x00 },
42 { S1DREG_COM_DISP_MODE, 0x00 },
43 { S1DREG_GPIO_CNF0, 0x00 },
44 { S1DREG_GPIO_CNF1, 0x00 },
45 { S1DREG_GPIO_CTL0, 0x00 },
46 { S1DREG_GPIO_CTL1, 0x00 },
47 { S1DREG_CLK_CNF, 0x02 },
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dste-db8520.dtsi9 operating-points = <1152000 0
10 800000 0
11 400000 0
12 200000 0>;
23 reg = <0x06000000 0x00f00000>;
29 reg = <0x06f00000 0x00100000>;
35 reg = <0x07000000 0x01000000>;
49 reg = <0x17f00000 0x00100000>;
H A Dste-db8500.dtsi9 operating-points = <998400 0
10 800000 0
11 400000 0
12 200000 0>;
23 reg = <0x06000000 0x00f00000>;
29 reg = <0x06f00000 0x00100000>;
35 reg = <0x07000000 0x01000000>;
49 reg = <0x17f00000 0x00100000>;
H A Dbcm953012hr.dts50 reg = <0x80000000 0x10000000>;
55 partition@0 {
57 reg = <0x00000000 0x00200000>;
62 reg = <0x00200000 0x00400000>;
66 reg = <0x00600000 0x00a00000>;
70 reg = <0x01000000 0x07000000>;
82 partition@0 {
84 reg = <0x00000000 0x000d0000>;
88 reg = <0x000d0000 0x00030000>;
92 reg = <0x00100000 0x00600000>;
[all …]
H A Dbcm953012k.dts48 reg = <0x80000000 0x10000000>;
53 nandcs@0 {
55 reg = <0>;
64 partition@0 {
66 reg = <0x00000000 0x00200000>;
71 reg = <0x00200000 0x00400000>;
75 reg = <0x00600000 0x00a00000>;
79 reg = <0x01000000 0x07000000>;
92 partition@0 {
94 reg = <0x00000000 0x000d0000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/edac/
H A Dfsl_ddr_edac.h27 #define FSL_MC_DDR_SDRAM_CFG 0x0110
28 #define FSL_MC_CS_BNDS_0 0x0000
29 #define FSL_MC_CS_BNDS_OFS 0x0008
31 #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
32 #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
33 #define FSL_MC_ECC_ERR_INJECT 0x0e08
34 #define FSL_MC_CAPTURE_DATA_HI 0x0e20
35 #define FSL_MC_CAPTURE_DATA_LO 0x0e24
36 #define FSL_MC_CAPTURE_ECC 0x0e28
37 #define FSL_MC_ERR_DETECT 0x0e40
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/wfx/
H A Dhwio.h30 #define CFG_ERR_SPI_FRAME 0x00000001 // only with SPI
31 #define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 // only with SDIO
32 #define CFG_ERR_BUF_UNDERRUN 0x00000002
33 #define CFG_ERR_DATA_IN_TOO_LARGE 0x00000004
34 #define CFG_ERR_HOST_NO_OUT_QUEUE 0x00000008
35 #define CFG_ERR_BUF_OVERRUN 0x00000010
36 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
37 #define CFG_ERR_HOST_NO_IN_QUEUE 0x00000040
38 #define CFG_ERR_HOST_CRC_MISS 0x00000080 // only with SDIO
39 #define CFG_SPI_IGNORE_CS 0x00000080 // only with SPI
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_ddr_sdram.h27 #define DDR3_RTT_OFF 0
34 #define DDR4_RTT_OFF 0
43 #define DDR2_RTT_OFF 0
73 #define FSL_DDR_ODT_NEVER 0x0
74 #define FSL_DDR_ODT_CS 0x1
75 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
76 #define FSL_DDR_ODT_OTHER_DIMM 0x3
77 #define FSL_DDR_ODT_ALL 0x4
78 #define FSL_DDR_ODT_SAME_DIMM 0x5
79 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dexynos-srom.yaml33 <bank-number> 0 <parent address of bank> <size>
37 "^.*@[0-3],[a-f0-9]+$":
50 typically 0 as this is the start of the bank.
74 Tacp: Page mode access cycle at Page mode (0 - 15)
75 Tcah: Address holding time after CSn (0 - 15)
76 Tcoh: Chip selection hold on OEn (0 - 15)
77 Tacc: Access cycle (0 - 31, the actual time is N + 1)
78 Tcos: Chip selection set-up before OEn (0 - 15)
79 Tacs: Address set-up before CSn (0 - 15)
96 reg = <0x12560000 0x14>;
[all …]
/OK3568_Linux_fs/u-boot/configs/
H A Drk3588-qnx_defconfig6 CONFIG_SYS_MALLOC_F_LEN=0x80000
30 CONFIG_BOOTDELAY=0
41 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
46 CONFIG_FASTBOOT_BUF_ADDR=0xc00800
47 CONFIG_FASTBOOT_BUF_SIZE=0x07000000
49 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
80 CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks…
159 CONFIG_DEBUG_UART_BASE=0xFEB50000
176 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
177 CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
[all …]
H A Drk3588_defconfig6 CONFIG_SYS_MALLOC_F_LEN=0x80000
31 CONFIG_BOOTDELAY=0
42 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
47 CONFIG_FASTBOOT_BUF_ADDR=0xc00800
48 CONFIG_FASTBOOT_BUF_SIZE=0x07000000
50 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
84 CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks…
180 CONFIG_DEBUG_UART_BASE=0xFEB50000
199 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
200 CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h13 #define REGS_AHB0_BASE 0x01C00000
14 #define REGS_AHB1_BASE 0x00800000
15 #define REGS_AHB2_BASE 0x03000000
16 #define REGS_APB0_BASE 0x06000000
17 #define REGS_APB1_BASE 0x07000000
18 #define REGS_RCPUS_BASE 0x08000000
20 #define SUNXI_SRAM_D_BASE 0x08100000
23 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
24 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
26 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dcache.h67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
69 #define L2CACHE_512KB 0x00 /* 512KB */
70 #define L2CACHE_256KB 0x01 /* 256KB */
71 #define L2CACHE_1MB 0x02 /* 1MB */
72 #define L2CACHE_NONE 0x03 /* NONE */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
88 #define IDC_ENABLE 0x02000000 /* Cache enable */
89 #define IDC_DISABLE 0x04000000 /* Cache disable */
90 #define IDC_LDLCK 0x06000000 /* Load and lock */
[all …]
H A Dcpm_85xx.h21 #define CPM_CR_RST ((uint)0x80000000)
22 #define CPM_CR_PAGE ((uint)0x7c000000)
23 #define CPM_CR_SBLOCK ((uint)0x03e00000)
24 #define CPM_CR_FLG ((uint)0x00010000)
25 #define CPM_CR_MCN ((uint)0x00003fc0)
26 #define CPM_CR_OPCODE ((uint)0x0000000f)
30 #define CPM_CR_SCC1_SBLOCK (0x04)
31 #define CPM_CR_SCC2_SBLOCK (0x05)
32 #define CPM_CR_SCC3_SBLOCK (0x06)
33 #define CPM_CR_SCC4_SBLOCK (0x07)
[all …]
/OK3568_Linux_fs/kernel/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/
H A Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/OK3568_Linux_fs/kernel/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dvf610twr.h44 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
51 #define CONFIG_FEC_MXC_PHYADDR 0
66 #define CONFIG_SYS_SPD_BUS_NUM 0
69 #define CONFIG_SYS_LOAD_ADDR 0x82000000
72 #define CONFIG_SYS_TEXT_BASE 0x3f408000
86 "bootm_size=0x07000000\0" \
87 "loadaddr=0x82000000\0" \
88 "kernel_addr_r=0x82000000\0" \
89 "fdt_addr=0x84000000\0" \
90 "fdt_addr_r=0x84000000\0" \
[all …]
H A Dls2080a_common.h21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
28 #define CONFIG_SYS_TEXT_BASE 0x80400000
30 #define CONFIG_SYS_TEXT_BASE 0x30100000
33 #define CONFIG_SYS_TEXT_BASE 0x20100000
34 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
35 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
36 #define CONFIG_ENV_SECT_SIZE 0x40000
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
56 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
[all …]
H A Ddevkit8000.h24 * header. That is 0x800FFFC0--0x80100000 should not be used for any
27 #define CONFIG_SYS_TEXT_BASE 0x80100000
29 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
30 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
32 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
33 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
54 #define CONFIG_DM9000_BASE 0x2c000000
56 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
79 #define CONFIG_JFFS2_PART_OFFSET 0x680000
80 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dsiul.h12 #define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
13 #define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
14 #define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
15 #define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
16 #define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
17 #define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
18 #define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
19 #define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
21 #define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
24 #define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
[all …]

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