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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h16 #define CCM_GPR0_OFFSET 0x0
17 #define CCM_OBSERVE0_OFFSET 0x0400
18 #define CCM_SCTRL0_OFFSET 0x0800
19 #define CCM_CCGR0_OFFSET 0x4000
20 #define CCM_ROOT0_TARGET_OFFSET 0x8000
59 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
61 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
66 uint32_t ctrl_24m; /* offset 0x0000 */
70 uint32_t rcosc_config0; /* offset 0x0010 */
74 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/mach-se/mach/
H A Dse7751.h19 #define PA_ROM 0x00000000 /* EPROM */
20 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
21 #define PA_FROM 0x01000000 /* EPROM */
22 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
23 #define PA_EXT1 0x04000000
24 #define PA_EXT1_SIZE 0x04000000
25 #define PA_EXT2 0x08000000
26 #define PA_EXT2_SIZE 0x04000000
27 #define PA_SDRAM 0x0c000000
28 #define PA_SDRAM_SIZE 0x04000000
[all …]
H A Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
H A Dse7343.h16 /* Area 0 */
17 #define PA_ROM 0x00000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
19 #define PA_FROM 0x00400000 /* Flash ROM */
20 #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
21 #define PA_SRAM 0x00800000 /* SRAM */
22 #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
24 #define PA_EXT1 0x04000000
25 #define PA_EXT1_SIZE 0x04000000
27 #define PA_EXT2 0x08000000
[all …]
H A Dse7721.h16 #define PA_ROM 0xa0000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
18 #define PA_FROM 0xa1000000 /* Flash-ROM */
19 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
20 #define PA_EXT1 0xa4000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
23 #define PA_SDRAM_SIZE 0x04000000
25 #define PA_EXT4 0xb0000000
26 #define PA_EXT4_SIZE 0x04000000
[all …]
H A Dse7722.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
23 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE 0x04000000
26 #define PA_EXT4 0xb0000000
27 #define PA_EXT4_SIZE 0x04000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts15 /memreserve/ 0x80000000 0x00010000;
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0x0 0x0>;
44 cpu-release-addr = <0x0 0x8000fff8>;
50 reg = <0x0 0x1>;
52 cpu-release-addr = <0x0 0x8000fff8>;
58 reg = <0x0 0x2>;
60 cpu-release-addr = <0x0 0x8000fff8>;
66 reg = <0x0 0x3>;
[all …]
H A Dvexpress-v2f-1xv7-ca53x2.dts20 arm,hbi = <0x247>;
21 arm,vexpress,site = <0xf>;
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0 0>;
54 reg = <0 1>;
65 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
73 /* Chipselect 2 is physically at 0x18000000 */
77 reg = <0 0x18000000 0 0x00800000>;
85 #address-cells = <0>;
[all …]
H A Dfoundation-v8.dtsi12 /memreserve/ 0x80000000 0x00010000;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
43 reg = <0x0 0x1>;
49 reg = <0x0 0x2>;
55 reg = <0x0 0x3>;
66 reg = <0x00000000 0x80000000 0 0x80000000>,
67 <0x00000008 0x80000000 0 0x80000000>;
89 reg = <0x0 0x2a440000 0 0x1000>,
[all …]
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x000>;
54 reg = <0x0 0x100>;
60 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
72 reg = <0x0 0x10000>;
78 reg = <0x0 0x10100>;
84 reg = <0x0 0x10200>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dsbc8548.dts20 reg = <0xe0000000 0x5000>;
23 ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
24 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
25 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
26 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
27 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
30 flash@0,0 {
34 reg = <0x0 0x0 0x800000>;
37 partition@0 {
40 reg = <0x00000000 0x007a0000>;
[all …]
H A Dsbc8548-altflash.dts23 reg = <0xe0000000 0x5000>;
26 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
27 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
28 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
29 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
30 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
32 flash@0,0 {
35 reg = <0x0 0x0 0x04000000>;
39 partition@0 {
42 reg = <0x00000000 0x03f00000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dvexpress-v2p-ca5s.dts16 arm,hbi = <0x225>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
55 reg = <0x80000000 0x40000000>;
63 /* Chipselect 2 is physically at 0x18000000 */
67 reg = <0x18000000 0x00800000>;
74 reg = <0x2a110000 0x1000>;
75 interrupts = <0 85 4>;
[all …]
H A Dvexpress-v2p-ca15-tc1.dts16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_ifc.h18 #define FSL_IFC_V1_1_0 0x01010000
19 #define FSL_IFC_V2_0_0 0x02000000
39 #define CSPR_BA 0xFFFF0000
41 #define CSPR_PORT_SIZE 0x00000180
44 #define CSPR_PORT_SIZE_8 0x00000080
46 #define CSPR_PORT_SIZE_16 0x00000100
48 #define CSPR_PORT_SIZE_32 0x00000180
50 #define CSPR_WP 0x00000040
53 #define CSPR_MSEL 0x00000006
56 #define CSPR_MSEL_NOR 0x00000000
[all …]
/OK3568_Linux_fs/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h23 #define SATA_HOST_CAP_S64A 0x80000000
24 #define SATA_HOST_CAP_SNCQ 0x40000000
25 #define SATA_HOST_CAP_SSNTF 0x20000000
26 #define SATA_HOST_CAP_SMPS 0x10000000
27 #define SATA_HOST_CAP_SSS 0x08000000
28 #define SATA_HOST_CAP_SALP 0x04000000
29 #define SATA_HOST_CAP_SAL 0x02000000
30 #define SATA_HOST_CAP_SCLO 0x01000000
31 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
33 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c19 * step: 0 goes through the initialization in one pass
36 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; in fsl_ddr_set_memctl_regs()
44 case 0: in fsl_ddr_set_memctl_regs()
74 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { in fsl_ddr_set_memctl_regs()
75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
76 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
77 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { in fsl_ddr_set_memctl_regs()
81 if (cs_ea > 0xeff) in fsl_ddr_set_memctl_regs()
82 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; in fsl_ddr_set_memctl_regs()
84 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; in fsl_ddr_set_memctl_regs()
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dbast.h16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)
17 #define BAST_CPLD_CTRL1_LRCADC (0x01)
18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)
19 #define BAST_CPLD_CTRL1_LRCARM (0x03)
20 #define BAST_CPLD_CTRL1_LRMASK (0x03)
24 #define BAST_CPLD_CTRL2_WNAND (0x04)
25 #define BAST_CPLD_CTLR2_IDERST (0x08)
29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)
30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)
34 #define BAST_CPLD_CTRL4_LLAT (0x01)
[all …]
/OK3568_Linux_fs/u-boot/board/terasic/de0-nano-soc/qts/
H A Diocsr_config.h16 0x00000000,
17 0x00000000,
18 0x0FF00000,
19 0xC0000000,
20 0x0000003F,
21 0x00008000,
22 0x00020080,
23 0x18060000,
24 0x08000000,
25 0x00018020,
[all …]
/OK3568_Linux_fs/u-boot/board/terasic/de10-nano/qts/
H A Diocsr_config.h16 0x00000000,
17 0x00000000,
18 0x0FF00000,
19 0xC0000000,
20 0x0000003F,
21 0x00008000,
22 0x00020080,
23 0x18060000,
24 0x08000000,
25 0x00018020,
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dsbc8641d.dts20 reg = <0x00000000 0x20000000>; // 512M at 0x0
24 reg = <0xf8005000 0x1000>;
26 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
27 1 0 0xf0000000 0x00010000 // 64KB EEPROM
28 2 0 0xf1000000 0x00100000 // EPLD (1MB)
29 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
30 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
31 6 0 0xf4000000 0x00100000 // LCD display (1MB)
32 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
34 flash@0,0 {
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen7_renderstate.c29 0x0000000c,
30 0x00000010,
31 0x00000018,
32 0x000001ec,
37 0x69040000,
38 0x61010008,
39 0x00000000,
40 0x00000001, /* reloc */
41 0x00000001, /* reloc */
42 0x00000000,
[all …]

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