Searched +full:0 +full:x02200000 (Results 1 – 19 of 19) sorted by relevance
14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)[all …]
16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)17 #define BAST_CPLD_CTRL1_LRCADC (0x01)18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)19 #define BAST_CPLD_CTRL1_LRCARM (0x03)20 #define BAST_CPLD_CTRL1_LRMASK (0x03)24 #define BAST_CPLD_CTRL2_WNAND (0x04)25 #define BAST_CPLD_CTLR2_IDERST (0x08)29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)34 #define BAST_CPLD_CTRL4_LLAT (0x01)[all …]
58 reg = <0x02200000 0x100000>;63 reg = <0x02280000 0x4000>;73 reg = <0x02284000 0x4000>;80 reg = <0x02290000 0x4000>;86 reg = <0x02288000 0x4000>;
17 #size-cells = <0>;19 cpu0: cpu@0 {22 reg = <0>;165 reg = <0x00900000 0x40000>;166 ranges = <0 0x00900000 0x40000>;176 #size-cells = <0>;178 reg = <0x02018000 0x4000>;179 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;192 reg = <0x02200000 0x4000>;193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;[all …]
48 #size-cells = <0>;50 cpu@0 {53 reg = <0x0>;85 #clock-cells = <0>;91 #clock-cells = <0>;99 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;104 #phy-cells = <0>;116 reg = <0x00900000 0x20000>;117 ranges = <0 0x00900000 0x20000>;127 reg = <0x00a01000 0x1000>,[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;97 #clock-cells = <0>;104 #clock-cells = <0>;111 #clock-cells = <0>;112 clock-frequency = <0>;118 #clock-cells = <0>;119 clock-frequency = <0>;125 #clock-cells = <0>;[all …]
77 reg = <0x02200000 0x4000>;78 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
10 #define OCRAM_BASE_ADDR 0x1000000011 #define OCRAM_SIZE 0x0001000012 #define OCRAM_BASE_S_ADDR 0x1001000013 #define OCRAM_S_SIZE 0x0001000015 #define CONFIG_SYS_IMMR 0x0100000016 #define CONFIG_SYS_DCSRBAR 0x2000000018 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)19 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)21 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)22 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)[all …]
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x8030000020 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */25 #define CONFIG_SYS_PAGE_SIZE 0x1000032 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */33 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */34 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */49 #define GICD_BASE 0x0600000050 #define GICR_BASE 0x0610000053 #define SMMU_BASE 0x05000000 /* GR0 Base */70 #define CCI_MN_BASE 0x04000000[all …]
13 #define CONFIG_SYS_IMMR 0x0100000014 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)15 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)16 #define CONFIG_SYS_FSL_DDR3_ADDR 0x0821000017 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)18 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)20 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)21 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)22 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)[all …]
12 #define CONFIG_SYS_IMMR 0x0100000013 #define CONFIG_SYS_DCSRBAR 0x2000000014 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)18 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)19 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)20 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)21 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)22 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)[all …]
12 #define ROMCP_ARB_BASE_ADDR 0x0000000013 #define ROMCP_ARB_END_ADDR 0x000FFFFF16 #define GPU_2D_ARB_BASE_ADDR 0x0220000017 #define GPU_2D_ARB_END_ADDR 0x02203FFF18 #define OPENVG_ARB_BASE_ADDR 0x0220400019 #define OPENVG_ARB_END_ADDR 0x02207FFF21 #define CAAM_ARB_BASE_ADDR 0x0010000022 #define CAAM_ARB_END_ADDR 0x00107FFF23 #define GPU_ARB_BASE_ADDR 0x0180000024 #define GPU_ARB_END_ADDR 0x01803FFF[all …]
23 #size-cells = <0>;25 cpu0: cpu@0 {28 reg = <0>;84 reg = <0x00900000 0x40000>;92 #size-cells = <0>;94 reg = <0x02018000 0x4000>;95 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;112 reg = <0x02200000 0x4000>;113 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;123 reg = <0x02204000 0x4000>;[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0>;88 reg = <0x00a01000 0x1000>,89 <0x00a02000 0x100>;94 #size-cells = <0>;96 ckil: clock@0 {98 reg = <0>;99 #clock-cells = <0>;107 #clock-cells = <0>;[all …]
54 #size-cells = <0>;56 cpu0: cpu@0 {59 reg = <0>;92 reg = <0x00a01000 0x1000>,93 <0x00a00100 0x100>;99 #size-cells = <0>;101 ckil: clock@0 {103 reg = <0>;104 #clock-cells = <0>;112 #clock-cells = <0>;[all …]
29 #define PHYS_SDRAM_1 0x034 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF000035 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000037 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0000038 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */47 #define CONFIG_SYS_TEXT_BASE 0x0800004049 #define CONFIG_SYS_TEXT_BASE 0x0100004085 * that the address here is incremented by 0x400 from the Base address86 * selected in QSys, since the SPI registers are at offset +0x400.87 * #define CONFIG_SYS_SPI_BASE 0xff240400[all …]
21 #define QE_DATAONLY_BASE 038 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */39 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */40 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */41 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */51 #define QE_CR_FLG 0x0001000052 #define QE_RESET 0x8000000053 #define QE_INIT_TX_RX 0x0000000054 #define QE_INIT_RX 0x0000000155 #define QE_INIT_TX 0x00000002[all …]
12 #define ARM_R0 029 #define ARM_COND_EQ 0x0 /* == */30 #define ARM_COND_NE 0x1 /* != */31 #define ARM_COND_CS 0x2 /* unsigned >= */33 #define ARM_COND_CC 0x3 /* unsigned < */35 #define ARM_COND_MI 0x4 /* < 0 */36 #define ARM_COND_PL 0x5 /* >= 0 */37 #define ARM_COND_VS 0x6 /* Signed Overflow */38 #define ARM_COND_VC 0x7 /* No Signed Overflow */39 #define ARM_COND_HI 0x8 /* unsigned > */[all …]
32 #define MEM_PART_SYSTEM 038 QE_CLK_NONE = 0,136 return 0; in cpm_muram_dma()228 return 0; in qe_alive_during_sleep()287 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */300 __be32 traps[16]; /* Trap addresses, 0 == ignore */344 #define BD_STATUS_MASK 0xffff0000345 #define BD_LENGTH_MASK 0x0000ffff353 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */354 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */[all …]