Searched +full:0 +full:x021b4000 (Results 1 – 12 of 12) sorted by relevance
44 reg = <0x021b0000 0x4000>;50 reg = <0x021b4000 0x4000>;
40 DATA 4 0x020E04bc 0x0000302842 DATA 4 0x020E04c0 0x0000302844 DATA 4 0x020E04c4 0x0000302846 DATA 4 0x020E04c8 0x0000302848 DATA 4 0x020E04cc 0x0000302850 DATA 4 0x020E04d0 0x0000302852 DATA 4 0x020E04d4 0x0000302854 DATA 4 0x020E04d8 0x0000302857 DATA 4 0x020E0470 0x0000003859 DATA 4 0x020E0474 0x00000038[all …]
35 DATA 4 0x020C4018 0x6032437 DATA 4 0x020E05a8 0x0000303838 DATA 4 0x020E05b0 0x0000303839 DATA 4 0x020E0524 0x0000303840 DATA 4 0x020E051c 0x0000303842 DATA 4 0x020E0518 0x0000303843 DATA 4 0x020E050c 0x0000303844 DATA 4 0x020E05b8 0x0000303845 DATA 4 0x020E05c0 0x0000303847 DATA 4 0x020E05ac 0x00000038[all …]
125 #define MX6SL_IOM_DDR_BASE 0x020e0300151 #define MX6SL_IOM_GRP_BASE 0x020e0500168 #define MX6UL_IOM_DDR_BASE 0x020e0200191 #define MX6UL_IOM_GRP_BASE 0x020e0400206 #define MX6SX_IOM_DDR_BASE 0x020e0200232 #define MX6SX_IOM_GRP_BASE 0x020e0500252 #define MX6DQ_IOM_DDR_BASE 0x020e0500287 #define MX6DQ_IOM_GRP_BASE 0x020e0700310 #define MX6SDL_IOM_DDR_BASE 0x020e0400343 #define MX6SDL_IOM_GRP_BASE 0x020e0700[all …]
44 #size-cells = <0>;46 cpu0: cpu@0 {49 reg = <0>;85 reg = <0x00a01000 0x1000>,86 <0x00a00100 0x100>;92 #size-cells = <0>;94 ckil: clock@0 {96 reg = <0>;97 #clock-cells = <0>;105 #clock-cells = <0>;[all …]
24 memory { device_type = "memory"; reg = <0 0>; };48 #size-cells = <0>;50 cpu@0 {53 reg = <0x0>;83 reg = <0x00a01000 0x1000>,84 <0x00a00100 0x100>;90 #size-cells = <0>;94 #clock-cells = <0>;100 #clock-cells = <0>;114 reg = <0x00900000 0x20000>;[all …]
53 #size-cells = <0>;57 #clock-cells = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;83 reg = <0x00110000 0x2000>;84 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,85 <0 13 IRQ_TYPE_LEVEL_HIGH>,86 <0 13 IRQ_TYPE_LEVEL_HIGH>,87 <0 13 IRQ_TYPE_LEVEL_HIGH>;[all …]
54 #size-cells = <0>;56 cpu0: cpu@0 {59 reg = <0>;92 reg = <0x00a01000 0x1000>,93 <0x00a00100 0x100>;99 #size-cells = <0>;101 ckil: clock@0 {103 reg = <0>;104 #clock-cells = <0>;112 #clock-cells = <0>;[all …]
45 #size-cells = <0>;47 cpu0: cpu@0 {50 reg = <0>;82 #clock-cells = <0>;89 #clock-cells = <0>;96 #clock-cells = <0>;97 clock-frequency = <0>;103 #clock-cells = <0>;104 clock-frequency = <0>;117 reg = <0x00900000 0x20000>;[all …]
48 #size-cells = <0>;50 cpu@0 {53 reg = <0x0>;85 #clock-cells = <0>;91 #clock-cells = <0>;99 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;104 #phy-cells = <0>;116 reg = <0x00900000 0x20000>;117 ranges = <0 0x00900000 0x20000>;127 reg = <0x00a01000 0x1000>,[all …]
55 #clock-cells = <0>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;74 #size-cells = <0>;79 lvds-channel@0 {81 #size-cells = <0>;82 reg = <0>;85 port@0 {86 reg = <0>;[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;97 #clock-cells = <0>;104 #clock-cells = <0>;111 #clock-cells = <0>;112 clock-frequency = <0>;118 #clock-cells = <0>;119 clock-frequency = <0>;125 #clock-cells = <0>;[all …]