Home
last modified time | relevance | path

Searched +full:0 +full:x01e00000 (Results 1 – 25 of 51) sorted by relevance

123

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h12 #define SUNXI_SRAM_A1_BASE 0x00000000
15 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
21 #define SUNXI_DE2_BASE 0x01000000
24 #define SUNXI_CPUCFG_BASE 0x01700000
27 #define SUNXI_SRAMC_BASE 0x01c00000
28 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h36 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
37 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
38 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
39 #define DAVINCI_UART0_BASE (0x01c20000)
40 #define DAVINCI_UART1_BASE (0x01c20400)
41 #define DAVINCI_TIMER3_BASE (0x01c20800)
42 #define DAVINCI_I2C_BASE (0x01c21000)
43 #define DAVINCI_TIMER0_BASE (0x01c21400)
44 #define DAVINCI_TIMER1_BASE (0x01c21800)
45 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
H A Dda8xx-usb.h19 #define DA8XX_USB_OTG_BASE 0x01E00000
22 #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
25 #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
54 #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
55 #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
56 #define DA8XX_USB_TXINT_SHIFT 0
59 #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
70 #define CFGCHIP2_NO_OVERRIDE (0 << 13)
83 #define CFGCHIP2_REFFREQ (0xf << 0)
84 #define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_qe.h21 #define QE_DATAONLY_BASE 0
38 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
39 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
40 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
41 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
51 #define QE_CR_FLG 0x00010000
52 #define QE_RESET 0x80000000
53 #define QE_INIT_TX_RX 0x00000000
54 #define QE_INIT_RX 0x00000001
55 #define QE_INIT_TX 0x00000002
[all …]
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dmeesc.h30 #define CONFIG_SYS_TEXT_BASE 0x21F00000
64 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
65 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
71 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
72 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
73 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
86 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
101 #define CONFIG_ET1100_BASE 0x70000000
106 #define CONFIG_ENV_OFFSET 0x4200
107 #define CONFIG_ENV_SIZE 0x4200
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-frontend.yaml70 const: 0
72 port@0:
107 reg = <0x01e00000 0x20000>;
117 #size-cells = <0>;
121 #size-cells = <0>;
124 fe0_out_be0: endpoint@0 {
125 reg = <0>;
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Dusb-da8xx.c24 #define DA8XX_USB0_BASE 0x01e00000
25 #define DA8XX_USB1_BASE 0x01e25000
103 [0] = {
H A Ddavinci.h38 #define DAVINCI_PLL1_BASE 0x01c40800
39 #define DAVINCI_PLL2_BASE 0x01c40c00
40 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
42 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
43 #define SYSMOD_VDAC_CONFIG 0x2c
44 #define SYSMOD_VIDCLKCTL 0x38
45 #define SYSMOD_VPSS_CLKCTL 0x44
46 #define SYSMOD_VDD3P3VPWDN 0x48
47 #define SYSMOD_VSCLKDIS 0x6c
48 #define SYSMOD_PUPDCTL1 0x7c
[all …]
H A Ddevices.c24 #define DAVINCI_I2C_BASE 0x01C21000
25 #define DAVINCI_ATA_BASE 0x01C66000
26 #define DAVINCI_MMCSD0_BASE 0x01E10000
27 #define DM355_MMCSD0_BASE 0x01E11000
28 #define DM355_MMCSD1_BASE 0x01E00000
29 #define DM365_MMCSD0_BASE 0x01D11000
30 #define DM365_MMCSD1_BASE 0x01D00000
37 0x800); in davinci_map_sysmod()
49 .end = DAVINCI_I2C_BASE + 0x40,
77 .end = DAVINCI_ATA_BASE + 0x7ff,
[all …]
/OK3568_Linux_fs/kernel/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c35 for (i = 0; i < 64; i++) { in gk104_top_oneinit()
39 type = ~0; in gk104_top_oneinit()
40 inst = 0; in gk104_top_oneinit()
43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_oneinit()
45 switch (data & 0x00000003) { in gk104_top_oneinit()
46 case 0x00000000: /* NOT_VALID */ in gk104_top_oneinit()
48 case 0x00000001: /* DATA */ in gk104_top_oneinit()
49 inst = (data & 0x3c000000) >> 26; in gk104_top_oneinit()
50 info->addr = (data & 0x00fff000); in gk104_top_oneinit()
51 if (data & 0x00000004) in gk104_top_oneinit()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/
H A Dts72xx.c71 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
72 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
83 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
84 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
86 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
101 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
110 .offset = 0,
129 .chip_offset = 0,
140 .start = 0, /* filled in later */
141 .end = 0, /* filled in later */
[all …]
/OK3568_Linux_fs/u-boot/arch/nios2/dts/
H A D3c120_devboard.dts19 #size-cells = <0>;
21 cpu: cpu@0x0 {
24 reg = <0x00000000>;
39 altr,reset-addr = <0xc2800000>;
40 altr,fast-tlb-miss-addr = <0xc7fff400>;
41 altr,exception-addr = <0xd0000020>;
47 memory@0 {
49 reg = <0x10000000 0x08000000>,
50 <0x07fff400 0x00000400>;
53 sopc@0 {
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dexynos5800-peach-pi.dts35 pwms = <&pwm 0 1000000 0>;
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
79 reg = <0x9>;
86 reg = <0x20>;
99 reg = <0x20>;
105 firmware_storage_spi: flash@0 {
106 reg = <0>;
112 elog-panic-event-offset = <0x01e00000 0x100000>;
114 elog-shrink-size = <0x400>;
115 elog-full-threshold = <0xc00>;
[all …]
H A Dexynos5420-peach-pit.dts36 pwms = <&pwm 0 1000000 0>;
37 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
67 reg = <0x9>;
74 reg = <0x20>;
80 reg = <0x48>;
84 0x02 0xa1 0x01 /* HPD low */
87 * [1:0] SW output 1.2V voltage is lower to 96%
89 0x04 0x14 0x01
94 0x04 0xe3 0x20
95 0x04 0xe2 0x80 /* [7] RCO SS enable */
[all …]
H A Dsun5i-a13.dtsi60 framebuffer@0 {
106 reg = <0x01c20060 0x8>;
108 clock-indices = <0>, <1>,
133 reg = <0x01c20068 0x4>;
135 clock-indices = <0>, <5>,
144 reg = <0x01c2006c 0x4>;
146 clock-indices = <0>, <1>,
158 reg = <0x01c20100 0x4>;
159 clocks = <&pll5 0>;
160 clock-indices = <0>,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
[all …]
/OK3568_Linux_fs/kernel/include/soc/fsl/qe/
H A Dqe.h32 #define MEM_PART_SYSTEM 0
38 QE_CLK_NONE = 0,
136 return 0; in cpm_muram_dma()
228 return 0; in qe_alive_during_sleep()
287 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
300 __be32 traps[16]; /* Trap addresses, 0 == ignore */
344 #define BD_STATUS_MASK 0xffff0000
345 #define BD_LENGTH_MASK 0x0000ffff
353 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
354 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram.h23 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
30 u32 dram_timing4; /* 0x10 */
35 u32 dram_addrw; /* 0x2c */
36 u32 dram_if_width; /* 0x30 */
40 u32 sbe_count; /* 0x40 */
44 u32 drop_addr; /* 0x50 */
48 u32 ctrl_width; /* 0x60 */
52 u32 rfifo_cmap; /* 0x70 */
56 u32 fpgaport_rst; /* 0x80 */
60 u32 prot_rule_addr; /* 0x90 */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie.txt46 "p2u-N": where N ranges from 0 to one less than the total number of lanes
49 0: C0
64 - cell 0 specifies the bus and device numbers of the root port:
67 - cell 1 denotes the upper 32 address bits and should be 0
80 - 0x81000000: I/O memory region
81 - 0x82000000: non-prefetchable memory region
82 - 0xc2000000: prefetchable memory region
103 - pinctrl-0: phandle for the 'default' state of pin configuration.
146 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
147 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mips-boards/
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h13 #define CONFIG_SYS_IMMR 0x01000000
14 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
15 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
16 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
17 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
18 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
20 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
21 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
22 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
[all …]

123