Searched +full:0 +full:x01d00000 (Results 1 – 16 of 16) sorted by relevance
42 alchemy_gpio_direction_output(4, 0); in gpr_reset()43 alchemy_gpio_direction_output(5, 0); in gpr_reset()48 alchemy_gpio_direction_output(1, 0); in gpr_reset()81 [0] = {91 .id = 0,99 * 0x00000000-0x00200000 : "kernel"100 * 0x00200000-0x00a00000 : "rootfs"101 * 0x01d00000-0x01f00000 : "config"102 * 0x01c00000-0x01d00000 : "yamon"103 * 0x01d00000-0x01d40000 : "yamon env vars"[all …]
9 #define DAVINCI_ASP0_BASE 0x01E0200010 #define DAVINCI_ASP1_BASE 0x01E0400013 #define DAVINCI_DM365_ASP0_BASE 0x01D0200016 #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D0100017 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D0180020 #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D0000023 #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D0400026 #define DAVINCI_DA830_MCASP2_REG_BASE 0x01D0800040 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
24 #define DAVINCI_I2C_BASE 0x01C2100025 #define DAVINCI_ATA_BASE 0x01C6600026 #define DAVINCI_MMCSD0_BASE 0x01E1000027 #define DM355_MMCSD0_BASE 0x01E1100028 #define DM355_MMCSD1_BASE 0x01E0000029 #define DM365_MMCSD0_BASE 0x01D1100030 #define DM365_MMCSD1_BASE 0x01D0000037 0x800); in davinci_map_sysmod()49 .end = DAVINCI_I2C_BASE + 0x40,77 .end = DAVINCI_ATA_BASE + 0x7ff,[all …]
72 #size-cells = <0>;74 cpu0: cpu@0 {77 reg = <0>;155 reg = <0x01400000 0x20000>;168 reg = <0x01c00000 0x1000>;175 reg = <0x01d00000 0x80000>;178 ranges = <0 0x01d00000 0x80000>;180 ve_sram: sram-section@0 {183 reg = <0x000000 0x80000>;190 reg = <0x01c0e000 0x1000>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
90 #size-cells = <0>;92 cpu0: cpu@0 {95 reg = <0>;111 #clock-cells = <0>;119 #clock-cells = <0>;135 reg = <0x01c00000 0x30>;142 reg = <0x01d00000 0x80000>;145 ranges = <0 0x01d00000 0x80000>;147 ve_sram: sram-section@0 {150 reg = <0x000000 0x80000>;[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
104 reg = <0x01d00000 0xff000>;
22 gpios = <&gpt2 0 1>;25 gpios = <&gpt3 0 1>;34 memory@0 {35 reg = <0x00000000 0x10000000>; // 256MB41 cell-index = <0>;87 phy0: ethernet-phy@0 {88 reg = <0>;95 reg = <0x50>;101 reg = <0x8000 0x4000>;106 interrupt-map-mask = <0xf800 0 0 7>;[all …]
23 memory@0 {24 reg = <0x00000000 0x08000000>; // 128MB30 cell-index = <0>;61 phy0: ethernet-phy@0 {62 reg = <0>;69 reg = <0x51>;73 reg = <0x52>;80 interrupt-map-mask = <0xf800 0 0 7>;81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot82 0xc000 0 0 2 &mpc5200_pic 1 1 3[all …]
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
36 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)37 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)38 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)39 #define DAVINCI_UART0_BASE (0x01c20000)40 #define DAVINCI_UART1_BASE (0x01c20400)41 #define DAVINCI_TIMER3_BASE (0x01c20800)42 #define DAVINCI_I2C_BASE (0x01c21000)43 #define DAVINCI_TIMER0_BASE (0x01c21400)44 #define DAVINCI_TIMER1_BASE (0x01c21800)45 #define DAVINCI_WDOG_BASE (0x01c21c00)[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]
30 reg = <0 0 0 0>;39 reg = <0x0 0x86000000 0x0 0x300000>;44 reg = <0x0 0x86300000 0x0 0x100000>;49 reg = <0x0 0x86400000 0x0 0x100000>;54 reg = <0x0 0x86500000 0x0 0x180000>;59 reg = <0x0 0x86680000 0x0 0x80000>;65 reg = <0x0 0x86700000 0x0 0xe0000>;72 reg = <0x0 0x867e0000 0x0 0x20000>;77 reg = <0x0 0x86800000 0x0 0x2b00000>;82 reg = <0x0 0x89300000 0x0 0x600000>;[all …]