Searched +full:0 +full:x01c20400 (Results 1 – 12 of 12) sorted by relevance
42 reg = <0x01c20400 0x400>;
14 #clock-cells = <0>;21 #clock-cells = <0>;44 reg = <0x01c00000 0x30>;51 reg = <0x00010000 0x1000>;54 ranges = <0 0x00010000 0x1000>;56 otg_sram: sram-section@0 {59 reg = <0x0000 0x1000>;67 reg = <0x01c20000 0x400>;76 reg = <0x01c20400 0x400>;83 reg = <0x01c20800 0x400>;[all …]
70 #size-cells = <0>;72 cpu@0 {75 reg = <0>;100 #clock-cells = <0>;108 #clock-cells = <0>;124 reg = <0x01000000 0x10000>;136 reg = <0x01100000 0x100000>;137 clocks = <&display_clocks 0>,141 resets = <&display_clocks 0>;145 #size-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
55 #size-cells = <0>;57 cpu@0 {60 reg = <0>;79 #clock-cells = <0>;86 #clock-cells = <0>;101 reg = <0x01c0f000 0x1000>;115 #size-cells = <0>;120 reg = <0x01c10000 0x1000>;134 #size-cells = <0>;139 reg = <0x01c11000 0x1000>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;78 #clock-cells = <0>;80 clock-frequency = <0>;84 #clock-cells = <0>;86 reg = <0x01c20050 0x4>;93 #clock-cells = <0>;100 osc32k: clk@0 {101 #clock-cells = <0>;[all …]
64 framebuffer@0 {110 #size-cells = <0>;111 cpu0: cpu@0 {114 reg = <0x0>;125 cooling-min-level = <0>;163 reg = <0x40000000 0x80000000>;178 #clock-cells = <0>;180 clock-frequency = <0>;184 #clock-cells = <0>;186 reg = <0x01c20050 0x4>;[all …]
36 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)37 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)38 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)39 #define DAVINCI_UART0_BASE (0x01c20000)40 #define DAVINCI_UART1_BASE (0x01c20400)41 #define DAVINCI_TIMER3_BASE (0x01c20800)42 #define DAVINCI_I2C_BASE (0x01c21000)43 #define DAVINCI_TIMER0_BASE (0x01c21400)44 #define DAVINCI_TIMER1_BASE (0x01c21800)45 #define DAVINCI_WDOG_BASE (0x01c21c00)[all …]