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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll1-clk.yaml17 const: 0
46 #clock-cells = <0>;
48 reg = <0x01c20000 0x4>;
55 #clock-cells = <0>;
57 reg = <0x01c20000 0x4>;
64 #clock-cells = <0>;
66 reg = <0x01c20000 0x4>;
H A Dallwinner,sun4i-a10-ccu.yaml130 reg = <0x01c20000 0x400>;
140 reg = <0x01f01400 0x100>;
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c40 #define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C)
41 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08)
42 #define SUN4I_SPI0_RX (0x01C05000 + 0x00)
43 #define SUN4I_SPI0_TX (0x01C05000 + 0x04)
44 #define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28)
45 #define SUN4I_SPI0_BC (0x01C05000 + 0x20)
46 #define SUN4I_SPI0_TC (0x01C05000 + 0x24)
48 #define SUN4I_CTL_ENABLE BIT(0)
58 #define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
59 #define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsuniv-f1c100s.dtsi14 #clock-cells = <0>;
21 #clock-cells = <0>;
44 reg = <0x01c00000 0x30>;
51 reg = <0x00010000 0x1000>;
54 ranges = <0 0x00010000 0x1000>;
56 otg_sram: sram-section@0 {
59 reg = <0x0000 0x1000>;
67 reg = <0x01c20000 0x400>;
76 reg = <0x01c20400 0x400>;
83 reg = <0x01c20800 0x400>;
[all …]
H A Dsun8i-v3s.dtsi70 #size-cells = <0>;
72 cpu@0 {
75 reg = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
124 reg = <0x01000000 0x10000>;
136 reg = <0x01100000 0x100000>;
137 clocks = <&display_clocks 0>,
141 resets = <&display_clocks 0>;
145 #size-cells = <0>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi90 #size-cells = <0>;
92 cpu0: cpu@0 {
95 reg = <0>;
111 #clock-cells = <0>;
119 #clock-cells = <0>;
135 reg = <0x01c00000 0x30>;
142 reg = <0x01d00000 0x80000>;
145 ranges = <0 0x01d00000 0x80000>;
147 ve_sram: sram-section@0 {
150 reg = <0x000000 0x80000>;
[all …]
H A Dsunxi-h3-h5.dtsi86 #clock-cells = <0>;
94 #clock-cells = <0>;
117 reg = <0x01000000 0x10000>;
128 compatible = "allwinner,sun8i-h3-de2-mixer-0";
129 reg = <0x01100000 0x100000>;
138 #size-cells = <0>;
152 reg = <0x01c02000 0x1000>;
162 reg = <0x01c0c000 0x1000>;
171 #size-cells = <0>;
173 tcon0_in: port@0 {
[all …]
H A Dsun8i-r40.dtsi63 #clock-cells = <0>;
71 #clock-cells = <0>;
81 #size-cells = <0>;
83 cpu0: cpu@0 {
86 reg = <0>;
117 polling-delay-passive = <0>;
118 polling-delay = <0>;
119 thermal-sensors = <&ths 0>;
124 polling-delay-passive = <0>;
125 polling-delay = <0>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
200 size = <0x6000000>;
201 alloc-ranges = <0x40000000 0x10000000>;
215 reg = <0x01c00000 0x30>;
220 sram_a: sram@0 {
222 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
H A Dsun6i-a31.dtsi100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
216 #clock-cells = <0>;
224 #clock-cells = <0>;
241 #clock-cells = <0>;
248 #clock-cells = <0>;
255 #clock-cells = <0>;
257 reg = <0x01c200d0 0x4>;
277 reg = <0x01c02000 0x1000>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h12 #define SUNXI_SRAM_A1_BASE 0x00000000
15 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
21 #define SUNXI_DE2_BASE 0x01000000
24 #define SUNXI_CPUCFG_BASE 0x01700000
27 #define SUNXI_SRAMC_BASE 0x01c00000
28 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h36 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
37 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
38 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
39 #define DAVINCI_UART0_BASE (0x01c20000)
40 #define DAVINCI_UART1_BASE (0x01c20400)
41 #define DAVINCI_TIMER3_BASE (0x01c20800)
42 #define DAVINCI_I2C_BASE (0x01c21000)
43 #define DAVINCI_TIMER0_BASE (0x01c21400)
44 #define DAVINCI_TIMER1_BASE (0x01c21800)
45 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/include/mach/
H A Dda8xx.h52 #define DA8XX_CP_INTC_BASE 0xfffee000
56 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
58 #define DA8XX_JTAG_ID_REG 0x18
59 #define DA8XX_HOST1CFG_REG 0x44
60 #define DA8XX_CHIPSIG_REG 0x174
61 #define DA8XX_CFGCHIP0_REG 0x17c
62 #define DA8XX_CFGCHIP1_REG 0x180
63 #define DA8XX_CFGCHIP2_REG 0x184
64 #define DA8XX_CFGCHIP3_REG 0x188
65 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun8i-v3s.dtsi55 #size-cells = <0>;
57 cpu@0 {
60 reg = <0>;
79 #clock-cells = <0>;
86 #clock-cells = <0>;
101 reg = <0x01c0f000 0x1000>;
115 #size-cells = <0>;
120 reg = <0x01c10000 0x1000>;
134 #size-cells = <0>;
139 reg = <0x01c11000 0x1000>;
[all …]
H A Dsun50i-a64.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
88 #clock-cells = <0>;
95 #clock-cells = <0>;
102 #clock-cells = <0>;
134 reg = <0x01c0f000 0x1000>;
143 #size-cells = <0>;
148 reg = <0x01c10000 0x1000>;
157 #size-cells = <0>;
[all …]
H A Dsun8i-h3.dtsi59 #size-cells = <0>;
61 cpu@0 {
64 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
115 #clock-cells = <0>;
125 reg = <0x01f01428 0x4>;
128 clock-indices = <0>, <1>;
134 reg = <0x01f01454 0x4>;
135 #clock-cells = <0>;
[all …]
H A Dsun8i-a23-a33.dtsi59 simplefb_lcd: framebuffer@0 {
63 clocks = <&pll6 0>;
81 #size-cells = <0>;
83 cpu@0 {
86 reg = <0>;
102 #clock-cells = <0>;
109 #clock-cells = <0>;
116 #clock-cells = <0>;
118 reg = <0x01c20000 0x4>;
125 #clock-cells = <0>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
78 #clock-cells = <0>;
80 clock-frequency = <0>;
84 #clock-cells = <0>;
86 reg = <0x01c20050 0x4>;
93 #clock-cells = <0>;
100 osc32k: clk@0 {
101 #clock-cells = <0>;
[all …]
H A Dsun5i-gr8.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
78 #clock-cells = <0>;
80 clock-frequency = <0>;
84 #clock-cells = <0>;
86 reg = <0x01c20050 0x4>;
93 #clock-cells = <0>;
100 osc32k: clk@0 {
101 #clock-cells = <0>;
[all …]
H A Dsun6i-a31.dtsi64 simplefb_hdmi: framebuffer@0 {
68 clocks = <&pll6 0>;
76 clocks = <&pll6 0>;
94 #size-cells = <0>;
96 cpu0: cpu@0 {
99 reg = <0>;
110 cooling-min-level = <0>;
166 reg = <0x40000000 0x80000000>;
183 #clock-cells = <0>;
188 osc32k: clk@0 {
[all …]
H A Dsun4i-a10.dtsi64 framebuffer@0 {
110 #size-cells = <0>;
111 cpu0: cpu@0 {
114 reg = <0x0>;
125 cooling-min-level = <0>;
163 reg = <0x40000000 0x80000000>;
178 #clock-cells = <0>;
180 clock-frequency = <0>;
184 #clock-cells = <0>;
186 reg = <0x01c20050 0x4>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64.dtsi46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug138 0x80000000 | 0xf0000000 | UART0
139 0x80004000 | 0xf0004000 | UART1
140 0x80008000 | 0xf0008000 | UART2
141 0x8000c000 | 0xf000c000 | UART3
142 0x80010000 | 0xf0010000 | UART4
143 0x80014000 | 0xf0014000 | UART5
144 0x80018000 | 0xf0018000 | UART6
145 0x8001c000 | 0xf001c000 | UART7
146 0x80020000 | 0xf0020000 | UART8
147 0x80024000 | 0xf0024000 | UART9
[all …]

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