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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml19 const: 0
128 const: 0
130 port@0:
141 "^endpoint(@[0-9])$":
164 - port@0
390 reg = <0x01c0c000 0x1000>;
401 #clock-cells = <0>;
406 #size-cells = <0>;
408 port@0 {
410 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h12 #define SUNXI_SRAM_A1_BASE 0x00000000
15 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
21 #define SUNXI_DE2_BASE 0x01000000
24 #define SUNXI_CPUCFG_BASE 0x01700000
27 #define SUNXI_SRAMC_BASE 0x01c00000
28 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun5i-a13.dtsi60 framebuffer@0 {
106 reg = <0x01c20060 0x8>;
108 clock-indices = <0>, <1>,
133 reg = <0x01c20068 0x4>;
135 clock-indices = <0>, <5>,
144 reg = <0x01c2006c 0x4>;
146 clock-indices = <0>, <1>,
158 reg = <0x01c20100 0x4>;
159 clocks = <&pll5 0>;
160 clock-indices = <0>,
[all …]
H A Dsun5i-gr8.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
78 #clock-cells = <0>;
80 clock-frequency = <0>;
84 #clock-cells = <0>;
86 reg = <0x01c20050 0x4>;
93 #clock-cells = <0>;
100 osc32k: clk@0 {
101 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun8i-v3s.dtsi70 #size-cells = <0>;
72 cpu@0 {
75 reg = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
124 reg = <0x01000000 0x10000>;
136 reg = <0x01100000 0x100000>;
137 clocks = <&display_clocks 0>,
141 resets = <&display_clocks 0>;
145 #size-cells = <0>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi90 #size-cells = <0>;
92 cpu0: cpu@0 {
95 reg = <0>;
111 #clock-cells = <0>;
119 #clock-cells = <0>;
135 reg = <0x01c00000 0x30>;
142 reg = <0x01d00000 0x80000>;
145 ranges = <0 0x01d00000 0x80000>;
147 ve_sram: sram-section@0 {
150 reg = <0x000000 0x80000>;
[all …]
H A Dsunxi-h3-h5.dtsi86 #clock-cells = <0>;
94 #clock-cells = <0>;
117 reg = <0x01000000 0x10000>;
128 compatible = "allwinner,sun8i-h3-de2-mixer-0";
129 reg = <0x01100000 0x100000>;
138 #size-cells = <0>;
152 reg = <0x01c02000 0x1000>;
162 reg = <0x01c0c000 0x1000>;
171 #size-cells = <0>;
173 tcon0_in: port@0 {
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
200 size = <0x6000000>;
201 alloc-ranges = <0x40000000 0x10000000>;
215 reg = <0x01c00000 0x30>;
220 sram_a: sram@0 {
222 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
H A Dsun6i-a31.dtsi100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
216 #clock-cells = <0>;
224 #clock-cells = <0>;
241 #clock-cells = <0>;
248 #clock-cells = <0>;
255 #clock-cells = <0>;
257 reg = <0x01c200d0 0x4>;
277 reg = <0x01c02000 0x1000>;
[all …]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
183 size = <0x6000000>;
184 alloc-ranges = <0x40000000 0x10000000>;
210 #clock-cells = <0>;
217 #clock-cells = <0>;
233 #clock-cells = <0>;
240 #clock-cells = <0>;
247 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64.dtsi46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
[all …]