Searched +full:0 +full:x01c02000 (Results 1 – 21 of 21) sorted by relevance
20 The first cell is either 0 or 1, the former to use the normal49 reg = <0x01c02000 0x1000>;
55 reg = <0x01c02000 0x1000>;56 interrupts = <0 50 4>;
80 reg = <0x01c02000 0x1000>;81 interrupts = <0 50 4>;
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
59 #size-cells = <0>;61 cpu@0 {64 reg = <0>;100 #clock-cells = <0>;107 #clock-cells = <0>;115 #clock-cells = <0>;125 reg = <0x01f01428 0x4>;128 clock-indices = <0>, <1>;134 reg = <0x01f01454 0x4>;135 #clock-cells = <0>;[all …]
59 simplefb_lcd: framebuffer@0 {63 clocks = <&pll6 0>;81 #size-cells = <0>;83 cpu@0 {86 reg = <0>;102 #clock-cells = <0>;109 #clock-cells = <0>;116 #clock-cells = <0>;118 reg = <0x01c20000 0x4>;125 #clock-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;78 #clock-cells = <0>;80 clock-frequency = <0>;84 #clock-cells = <0>;86 reg = <0x01c20050 0x4>;93 #clock-cells = <0>;100 osc32k: clk@0 {101 #clock-cells = <0>;[all …]
64 simplefb_hdmi: framebuffer@0 {68 clocks = <&pll6 0>;76 clocks = <&pll6 0>;94 #size-cells = <0>;96 cpu0: cpu@0 {99 reg = <0>;110 cooling-min-level = <0>;166 reg = <0x40000000 0x80000000>;183 #clock-cells = <0>;188 osc32k: clk@0 {[all …]
64 framebuffer@0 {110 #size-cells = <0>;111 cpu0: cpu@0 {114 reg = <0x0>;125 cooling-min-level = <0>;163 reg = <0x40000000 0x80000000>;178 #clock-cells = <0>;180 clock-frequency = <0>;184 #clock-cells = <0>;186 reg = <0x01c20050 0x4>;[all …]
66 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;119 cooling-min-level = <0>;163 reg = <0x40000000 0x80000000>;186 #clock-cells = <0>;188 reg = <0x01c20050 0x4>;194 #clock-cells = <0>;202 osc32k: clk@0 {[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
90 #size-cells = <0>;92 cpu0: cpu@0 {95 reg = <0>;111 #clock-cells = <0>;119 #clock-cells = <0>;135 reg = <0x01c00000 0x30>;142 reg = <0x01d00000 0x80000>;145 ranges = <0 0x01d00000 0x80000>;147 ve_sram: sram-section@0 {150 reg = <0x000000 0x80000>;[all …]
86 #clock-cells = <0>;94 #clock-cells = <0>;117 reg = <0x01000000 0x10000>;128 compatible = "allwinner,sun8i-h3-de2-mixer-0";129 reg = <0x01100000 0x100000>;138 #size-cells = <0>;152 reg = <0x01c02000 0x1000>;162 reg = <0x01c0c000 0x1000>;171 #size-cells = <0>;173 tcon0_in: port@0 {[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
65 #size-cells = <0>;67 cpu0: cpu@0 {73 reg = <0x0>;82 reg = <0x1>;91 reg = <0x2>;100 reg = <0x3>;109 reg = <0x100>;118 reg = <0x101>;127 reg = <0x102>;136 reg = <0x103>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;216 #clock-cells = <0>;224 #clock-cells = <0>;241 #clock-cells = <0>;248 #clock-cells = <0>;255 #clock-cells = <0>;257 reg = <0x01c200d0 0x4>;277 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]