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/OK3568_Linux_fs/kernel/arch/mips/include/asm/sn/sn0/
H A Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/OK3568_Linux_fs/kernel/arch/mips/alchemy/
H A Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d00000-0x01f00000 : "config"
102 * 0x01c00000-0x01d00000 : "yamon"
103 * 0x01d00000-0x01d40000 : "yamon env vars"
[all …]
H A Dboard-mtx1.c41 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); in mtx1_reset()
57 alchemy_gpio_direction_output(204, 0); in board_setup()
64 alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR); in board_setup()
65 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ in board_setup()
68 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ in board_setup()
72 alchemy_gpio_direction_output(212, 0); /* red off */ in board_setup()
105 .dev_id = "mtx1-wdt.0",
115 .id = 0,
144 .size = 0x01C00000,
145 .offset = 0,
[all …]
/OK3568_Linux_fs/device/rockchip/.chips/rk3588/
H A Dparameter.txt5 MAGIC: 0x5041524B
6 ATAG: 0x00200800
7 MACHINE: 0xffffffff
8 CHECK_MASK: 0x80
9 PWR_HLD: 0,0,A,0,1
11 GROW_ALIGN: 0
12 …0x00002000@0x00004000(uboot),0x00002000@0x00006000(misc),0x00020000@0x00008000(boot),0x00040000@0x…
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/include/mach/
H A Dhardware.h25 #define IO_PHYS UL(0x01c00000)
26 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
27 #define IO_SIZE 0x00400000
/OK3568_Linux_fs/u-boot/configs/
H A Dam43xx_hs_evm_defconfig4 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
10 CONFIG_ISW_ENTRY_ADDR=0x403018e0
11 CONFIG_SPL_STACK_R_ADDR=0x82000000
68 CONFIG_USB_GADGET_VENDOR_NUM=0x0403
69 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
H A Dam57xx_hs_evm_defconfig4 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
14 CONFIG_SPL_STACK_R_ADDR=0x82000000
34 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
35 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
80 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
81 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
H A Ddra7xx_hs_evm_defconfig4 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
14 CONFIG_SPL_STACK_R_ADDR=0x82000000
34 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
35 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
97 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
98 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
/OK3568_Linux_fs/u-boot/include/configs/
H A Dmk808_rk3066.h13 "mtdparts=rockchip-nand.0:" \
30 "idb raw 0x0 0x400000;" \
31 "idb.backup raw 0x400000 0x400000;" \
32 "spl raw 0x800000 0x400000;" \
33 "spl.backup1 raw 0xC00000 0x400000;" \
34 "spl.backup2 raw 0x1000000 0x400000;" \
35 "spl.backup3 raw 0x1400000 0x400000;" \
36 "spl.backup4 raw 0x1800000 0x400000;" \
37 "u-boot raw 0x1C00000 0x400000;" \
38 "u-boot.backup raw 0x2000000 0x400000;" \
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dsyscon.yaml84 reg = <0x01c00000 0x1000>;
90 reg = <0x020e0000 0x38>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mcde/
H A Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-rc32434/
H A Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
82 #define DMA_STAT_FINI (1 << 0)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h13 #define REGS_AHB0_BASE 0x01C00000
14 #define REGS_AHB1_BASE 0x00800000
15 #define REGS_AHB2_BASE 0x03000000
16 #define REGS_APB0_BASE 0x06000000
17 #define REGS_APB1_BASE 0x07000000
18 #define REGS_RCPUS_BASE 0x08000000
20 #define SUNXI_SRAM_D_BASE 0x08100000
23 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
24 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
26 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
H A Dcpu_sun4i.h12 #define SUNXI_SRAM_A1_BASE 0x00000000
15 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
21 #define SUNXI_DE2_BASE 0x01000000
24 #define SUNXI_CPUCFG_BASE 0x01700000
27 #define SUNXI_SRAMC_BASE 0x01c00000
28 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsuniv-f1c100s.dtsi14 #clock-cells = <0>;
21 #clock-cells = <0>;
44 reg = <0x01c00000 0x30>;
51 reg = <0x00010000 0x1000>;
54 ranges = <0 0x00010000 0x1000>;
56 otg_sram: sram-section@0 {
59 reg = <0x0000 0x1000>;
67 reg = <0x01c20000 0x400>;
76 reg = <0x01c20400 0x400>;
83 reg = <0x01c20800 0x400>;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sram/
H A Dallwinner,sun4i-a10-system-control.yaml132 reg = <0x01c00000 0x30>;
137 sram_a: sram@0 {
139 reg = <0x00000000 0xc000>;
142 ranges = <0 0x00000000 0xc000>;
146 reg = <0x8000 0x4000>;
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Ddm646x.c39 #define DAVINCI_VPIF_BASE (0x01C12000)
42 BIT_MASK(0))
46 #define DM646X_EMAC_BASE 0x01c80000
47 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
48 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
49 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
50 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
51 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
109 .id = 0,
122 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
[all …]
H A Ddm644x.c43 #define DM644X_EMAC_BASE 0x01c80000
44 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
45 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
46 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
47 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
48 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
91 .id = 0,
104 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
105 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
106 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
[all …]
H A Ddm355.c41 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
42 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
43 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
54 .start = 0x01c66000,
55 .end = 0x01c667ff,
73 .id = 0,
90 if (chipselect_mask & BIT(0)) in dm355_init_spi0()
102 #define INTMUX 0x18
103 #define EVTMUX 0x1c
113 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j721e-som-p0.dtsi14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15 <0x00000008 0x80000000 0x00000000 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa6000000 0x00 0x100000>;
37 reg = <0x00 0xa6100000 0x00 0xf00000>;
43 reg = <0x00 0xa7000000 0x00 0x100000>;
49 reg = <0x00 0xa7100000 0x00 0xf00000>;
55 reg = <0x00 0xa8000000 0x00 0x100000>;
61 reg = <0x00 0xa8100000 0x00 0xf00000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h37 for (x = 0; x < 100000; x++) \
50 #define LOONGSON_FLASH_BASE 0x1c000000
51 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
54 #define LOONGSON_LIO0_BASE 0x1e000000
55 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
58 #define LOONGSON_BOOT_BASE 0x1fc00000
59 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
61 #define LOONGSON_REG_BASE 0x1fe00000
62 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
65 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_qe.h21 #define QE_DATAONLY_BASE 0
38 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
39 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
40 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
41 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
51 #define QE_CR_FLG 0x00010000
52 #define QE_RESET 0x80000000
53 #define QE_INIT_TX_RX 0x00000000
54 #define QE_INIT_RX 0x00000001
55 #define QE_INIT_TX 0x00000002
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h51 for (x = 0; x < 100000; x++) \
69 #define LOONGSON_FLASH_BASE 0x1c000000
70 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
73 #define LOONGSON_LIO0_BASE 0x1e000000
74 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
77 #define LOONGSON_BOOT_BASE 0x1fc00000
78 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_REG_BASE 0x1fe00000
81 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
84 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]

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