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/OK3568_Linux_fs/kernel/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h10 #define MPC83XX_SCCR_OFFS 0xA08
11 #define MPC83XX_SCCR_USB_MASK 0x00f00000
12 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
13 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
14 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
15 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
16 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
17 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
18 #define MPC8315_SCCR_USB_MASK 0x00c00000
19 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/OK3568_Linux_fs/device/rockchip/.chips/OK3568/
H A Dparameter-buildroot-fit-ab.txt5 MAGIC: 0x5041524B
6 ATAG: 0x00200800
7 MACHINE: 0xffffffff
8 CHECK_MASK: 0x80
9 PWR_HLD: 0,0,A,0,1
11 GROW_ALIGN: 0
12 …0x00002000@0x00004000(uboot),0x00002000@0x00006000(misc),0x00020000@0x00008000(boot_a),0x00020000@…
H A Dparameter-buildroot-fit.txt5 MAGIC: 0x5041524B
6 ATAG: 0x00200800
7 MACHINE: 0xffffffff
8 CHECK_MASK: 0x80
9 PWR_HLD: 0,0,A,0,1
11 GROW_ALIGN: 0
12 …0x00002000@0x00004000(uboot),0x00002000@0x00006000(misc),0x00020000@0x00008000(boot),0x00040000@0x…
/OK3568_Linux_fs/device/rockchip/.chips/rk3566_rk3568/
H A Dparameter-buildroot-fit-ab.txt5 MAGIC: 0x5041524B
6 ATAG: 0x00200800
7 MACHINE: 0xffffffff
8 CHECK_MASK: 0x80
9 PWR_HLD: 0,0,A,0,1
11 GROW_ALIGN: 0
12 …0x00002000@0x00004000(uboot),0x00002000@0x00006000(misc),0x00020000@0x00008000(boot_a),0x00020000@…
H A Dparameter-buildroot-fit.txt5 MAGIC: 0x5041524B
6 ATAG: 0x00200800
7 MACHINE: 0xffffffff
8 CHECK_MASK: 0x80
9 PWR_HLD: 0,0,A,0,1
11 GROW_ALIGN: 0
12 …0x00002000@0x00004000(uboot),0x00002000@0x00006000(misc),0x00020000@0x00008000(boot),0x00040000@0x…
/OK3568_Linux_fs/u-boot/include/configs/
H A Drk3562_common.h13 #define CONFIG_SPL_TEXT_BASE 0x00000000
14 #define CONFIG_SPL_MAX_SIZE 0x00040000
15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
17 #define CONFIG_SPL_STACK 0x03fe0000
24 #define CONFIG_SYS_TEXT_BASE 0x00000000
26 #define CONFIG_SYS_TEXT_BASE 0x00200000
29 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
30 #define CONFIG_SYS_LOAD_ADDR 0x00c00800
34 #define GICD_BASE 0xfe901000
[all …]
H A Drk3568_common.h13 #define CONFIG_SPL_TEXT_BASE 0x00000000
14 #define CONFIG_SPL_MAX_SIZE 0x00040000
15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
17 #define CONFIG_SPL_STACK 0x03fe0000
24 #define CONFIG_SYS_TEXT_BASE 0x00000000
26 #define CONFIG_SYS_TEXT_BASE 0x00a00000
29 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
30 #define CONFIG_SYS_LOAD_ADDR 0x00c00800
34 #define GICD_BASE 0xfd400000
[all …]
H A Drk3528_common.h13 #define CONFIG_SPL_TEXT_BASE 0x00000000
14 #define CONFIG_SPL_MAX_SIZE 0x00040000
15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
17 #define CONFIG_SPL_STACK 0x03fe0000
24 #define CONFIG_SYS_TEXT_BASE 0x00000000
26 #define CONFIG_SYS_TEXT_BASE 0x00200000
29 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
30 #define CONFIG_SYS_LOAD_ADDR 0x00c00800
34 #define GICD_BASE 0xfed01000
[all …]
H A Drv1106_common.h17 #define CONFIG_SYS_TEXT_BASE 0x00200000
18 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
19 #define CONFIG_SYS_LOAD_ADDR 0x00e00800
21 #define GICD_BASE 0xff1f1000
22 #define GICC_BASE 0xff1f2000
23 #define CONFIG_SYS_SDRAM_BASE 0
24 #define SDRAM_MAX_SIZE 0xff000000
31 #define CONFIG_SPL_TEXT_BASE 0x00000000
32 #define CONFIG_SPL_MAX_SIZE 0x30000
33 #define CONFIG_SPL_BSS_START_ADDR 0x001fe000
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dmpc83xx.h24 #define EXC_OFF_SYS_RESET 0x0100
32 #define CONFIG_DEFAULT_IMMR 0xFF400000
35 #define IMMRBAR 0x0000
36 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
43 #define LBLAWBAR0 0x0020
44 #define LBLAWAR0 0x0024
45 #define LBLAWBAR1 0x0028
46 #define LBLAWAR1 0x002C
47 #define LBLAWBAR2 0x0030
48 #define LBLAWAR2 0x0034
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h136 #define CLKMGR_CTRL_SAFEMODE BIT(0)
137 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
147 #define CLKMGR_BYPASS_MAINPLL BIT(0)
148 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0
157 #define CLKMGR_STAT_BUSY BIT(0)
160 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0)
161 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
163 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
167 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
168 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dat91-sama5d2_xplained.dts17 atmel,vbus-gpio = <&pioA 42 0>;
19 pinctrl-0 = <&pinctrl_usb_default>;
30 pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
38 pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
47 flash@0 {
49 reg = <0>;
53 pinctrl-0 = <&pinctrl_qspi0_default>;
58 reg = <0x00000000 0x00c00000>;
63 reg = <0x00c00000 0x00000000>;
69 cs-gpios = <&pioA 17 0>, <0>, <0>, <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-i2c.c18 #define CX18_REG_I2C_1_WR 0xf15000
19 #define CX18_REG_I2C_1_RD 0xf15008
20 #define CX18_REG_I2C_2_WR 0xf25100
21 #define CX18_REG_I2C_2_RD 0xf25108
23 #define SETSCL_BIT 0x0001
24 #define SETSDL_BIT 0x0002
25 #define GETSCL_BIT 0x0004
26 #define GETSDL_BIT 0x0008
28 #define CX18_CS5345_I2C_ADDR 0x4c
29 #define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h18 #define PORT_CPM 0
24 #define USB_MAX_CTRL_PAYLOAD 0x4000
31 #define USB_DIR_BOTH 0x88
32 #define R_BUF_MAXSIZE 0x800
36 #define USB_MODE_EN 0x01
37 #define USB_MODE_HOST 0x02
38 #define USB_MODE_TEST 0x04
39 #define USB_MODE_SFTE 0x08
40 #define USB_MODE_RESUME 0x40
41 #define USB_MODE_LSS 0x80
[all …]
/OK3568_Linux_fs/buildroot/board/arm/juno/
H A Dreadme.txt88 NOR3ADDRESS: 0x00C00000 ;Image Flash Address
101 NOR3ADDRESS: 0x00C00000 ;Image Flash Address
114 NOR3ADDRESS: 0x02000000 ;Image Flash Address
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dm5272.h21 #define GPIO_PACNT_PA15MSK (0xC0000000)
22 #define GPIO_PACNT_DGNT1 (0x40000000)
23 #define GPIO_PACNT_PA14MSK (0x30000000)
24 #define GPIO_PACNT_DREQ1 (0x10000000)
25 #define GPIO_PACNT_PA13MSK (0x0C000000)
26 #define GPIO_PACNT_DFSC3 (0x04000000)
27 #define GPIO_PACNT_PA12MSK (0x03000000)
28 #define GPIO_PACNT_DFSC2 (0x01000000)
29 #define GPIO_PACNT_PA11MSK (0x00C00000)
30 #define GPIO_PACNT_QSPI_CS1 (0x00800000)
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dbluestone.dts16 dcr-parent = <&{/cpus/cpu@0}>;
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
/OK3568_Linux_fs/output/sessions/2025-06-05_23-17-21/
H A Dpart-table
/OK3568_Linux_fs/output/sessions/2025-06-06_01-57-56/
H A Dpart-table
/OK3568_Linux_fs/kernel/drivers/net/ethernet/ibm/emac/
H A Dmal.h37 #define MAL_CFG 0x00
38 #define MAL_CFG_SR 0x80000000
39 #define MAL_CFG_PLBB 0x00004000
40 #define MAL_CFG_OPBBL 0x00000080
41 #define MAL_CFG_EOPIE 0x00000004
42 #define MAL_CFG_LEA 0x00000002
43 #define MAL_CFG_SD 0x00000001
46 #define MAL1_CFG_PLBP_MASK 0x00c00000
47 #define MAL1_CFG_PLBP_10 0x00800000
48 #define MAL1_CFG_GA 0x00200000
[all …]
H A Demac.h103 #define EMAC_MR0_RXI 0x80000000
104 #define EMAC_MR0_TXI 0x40000000
105 #define EMAC_MR0_SRST 0x20000000
106 #define EMAC_MR0_TXE 0x10000000
107 #define EMAC_MR0_RXE 0x08000000
108 #define EMAC_MR0_WKE 0x04000000
111 #define EMAC_MR1_FDE 0x80000000
112 #define EMAC_MR1_ILE 0x40000000
113 #define EMAC_MR1_VLE 0x20000000
114 #define EMAC_MR1_EIFC 0x10000000
[all …]
/OK3568_Linux_fs/kernel/drivers/dma/
H A Dfsldma.h19 #define FSL_DMA_MR_CS 0x00000001
20 #define FSL_DMA_MR_CC 0x00000002
21 #define FSL_DMA_MR_CA 0x00000008
22 #define FSL_DMA_MR_EIE 0x00000040
23 #define FSL_DMA_MR_XFE 0x00000020
24 #define FSL_DMA_MR_EOLNIE 0x00000100
25 #define FSL_DMA_MR_EOLSIE 0x00000080
26 #define FSL_DMA_MR_EOSIE 0x00000200
27 #define FSL_DMA_MR_CDSM 0x00000010
28 #define FSL_DMA_MR_CTM 0x00000004
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/halrf/rtl8822c/
H A Dhalrf_tssi_8822c.c48 for (i = 0; i < reg_num; i++) { in _backup_bb_registers_8822c()
51 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", in _backup_bb_registers_8822c()
66 for (i = 0; i < reg_num; i++) { in _reload_bb_registers_8822c()
68 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", in _reload_bb_registers_8822c()
78 u8 tssi_rate = 0; in _halrf_driver_rate_to_tssi_rate_8822c()
83 tssi_rate = 0; in _halrf_driver_rate_to_tssi_rate_8822c()
118 u8 driver_rate = 0; in _halrf_tssi_rate_to_driver_rate_8822c()
122 if (rate == 0) in _halrf_tssi_rate_to_driver_rate_8822c()
158 #if 0 in _halrf_calculate_txagc_codeword_8822c()
165 for (i = 0; i < TSSI_CODE_NUM; i++) { in _halrf_calculate_txagc_codeword_8822c()
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h19 #define BR0 0x5000 /* Register offset to immr */
20 #define BR1 0x5008
21 #define BR2 0x5010
22 #define BR3 0x5018
23 #define BR4 0x5020
24 #define BR5 0x5028
25 #define BR6 0x5030
26 #define BR7 0x5038
28 #define BR_BA 0xFFFF8000
30 #define BR_XBA 0x00006000
[all …]
/OK3568_Linux_fs/u-boot/spl/include/
H A Dautoconf.mk

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