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/OK3568_Linux_fs/kernel/include/linux/ssb/
H A Dssb_driver_extif.h24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/fsp/
H A Dfsp_fv.h12 #define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
13 #define EFI_FV_FILE_ATTR_FIXED 0x00000100
14 #define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
17 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
18 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
19 #define EFI_FVB2_READ_STATUS 0x00000004
20 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
21 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
22 #define EFI_FVB2_WRITE_STATUS 0x00000020
23 #define EFI_FVB2_LOCK_CAP 0x00000040
[all …]
/OK3568_Linux_fs/kernel/arch/microblaze/include/asm/
H A Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dserial_pnx8xxx.h20 #define PNX8XXX_LCR 0
21 #define PNX8XXX_MCR 0x004
22 #define PNX8XXX_BAUD 0x008
23 #define PNX8XXX_CFG 0x00c
24 #define PNX8XXX_FIFO 0x028
25 #define PNX8XXX_ISTAT 0xfe0
26 #define PNX8XXX_IEN 0xfe4
27 #define PNX8XXX_ICLR 0xfe8
28 #define PNX8XXX_ISET 0xfec
29 #define PNX8XXX_PD 0xff4
[all …]
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dimmap_5271.h13 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
14 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
15 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
16 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
17 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
18 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
19 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
20 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
21 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
22 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
/OK3568_Linux_fs/kernel/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dgt215.c32 u32 tach = nvkm_rd32(device, 0x00e728) & 0x0000ffff; in gt215_therm_fan_sense()
33 u32 ctrl = nvkm_rd32(device, 0x00e720); in gt215_therm_fan_sense()
34 if (ctrl & 0x00000001) in gt215_therm_fan_sense()
48 nvkm_mask(device, 0x00e720, 0x00000003, 0x00000002); in gt215_therm_init()
50 nvkm_wr32(device, 0x00e724, device->crystal * 1000); in gt215_therm_init()
51 nvkm_mask(device, 0x00e720, 0x001f0000, tach->line << 16); in gt215_therm_init()
52 nvkm_mask(device, 0x00e720, 0x00000001, 0x00000001); in gt215_therm_init()
54 nvkm_mask(device, 0x00e720, 0x00000002, 0x00000000); in gt215_therm_init()
/OK3568_Linux_fs/kernel/sound/soc/mxs/
H A Dmxs-saif.h10 #define SAIF_CTRL 0x0
11 #define SAIF_STAT 0x10
12 #define SAIF_DATA 0x20
13 #define SAIF_VERSION 0X30
16 #define BM_SAIF_CTRL_SFTRST 0x80000000
17 #define BM_SAIF_CTRL_CLKGATE 0x40000000
19 #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
22 #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
23 #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
24 #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml44 "^emc-timings-[0-9]+$":
53 "^timing-[0-9]+$":
114 reg = <0x70019000 0x1000>;
118 interrupts = <0 77 4>;
130 0x40040001 /* MC_EMEM_ARB_CFG */
131 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
132 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
133 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
134 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
135 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
[all …]
H A Dnvidia,tegra30-mc.yaml61 "^emc-timings-[0-9]+$":
70 "^timing-[0-9]+$":
130 reg = <0x7000f000 0x400>;
134 interrupts = <0 77 4>;
146 0x0000000a /* MC_EMEM_ARB_CFG */
147 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
148 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
149 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
150 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
151 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
[all …]
/OK3568_Linux_fs/kernel/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/OK3568_Linux_fs/kernel/arch/arm/nwfpe/
H A Dfpsr.h32 #define MASK_SYSID 0xff000000
33 #define BIT_HARDWARE 0x80000000
34 #define FP_EMULATOR 0x01000000 /* System ID for emulator */
35 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
40 #define MASK_TRAP_ENABLE 0x00ff0000
41 #define MASK_TRAP_ENABLE_STRICT 0x001f0000
42 #define BIT_IXE 0x00100000 /* inexact exception enable */
43 #define BIT_UFE 0x00080000 /* underflow exception enable */
44 #define BIT_OFE 0x00040000 /* overflow exception enable */
45 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
[all …]
/OK3568_Linux_fs/kernel/arch/alpha/lib/
H A Dstacktrace.c6 #define MAJOR_OP 0xfc000000
7 #define LDA_OP 0x20000000
8 #define STQ_OP 0xb4000000
9 #define BR_OP 0xc0000000
11 #define STK_ALLOC_1 0x23de8000 /* lda $30,-X($30) */
12 #define STK_ALLOC_1M 0xffff8000
13 #define STK_ALLOC_2 0x43c0153e /* subq $30,X,$30 */
14 #define STK_ALLOC_2M 0xffe01fff
16 #define MEM_REG 0x03e00000
17 #define MEM_BASE 0x001f0000
[all …]
/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-ep93xx.c15 #define EP93XX_RTC_DATA 0x000
16 #define EP93XX_RTC_MATCH 0x004
17 #define EP93XX_RTC_STATUS 0x008
18 #define EP93XX_RTC_STATUS_INTR BIT(0)
19 #define EP93XX_RTC_LOAD 0x00C
20 #define EP93XX_RTC_CONTROL 0x010
21 #define EP93XX_RTC_CONTROL_MIE BIT(0)
22 #define EP93XX_RTC_SWCOMP 0x108
23 #define EP93XX_RTC_SWCOMP_DEL_MASK 0x001f0000
25 #define EP93XX_RTC_SWCOMP_INT_MASK 0x0000ffff
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dlpc.asl7 /* Intel LPC Bus Device - 0:1f.0 */
11 Name(_ADR, 0x001f0000)
13 OperationRegion(PRTX, PCI_Config, 0x60, 8)
33 Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
43 IO(Decode16, 0x20, 0x20, 0x01, 0x02)
44 IO(Decode16, 0x24, 0x24, 0x01, 0x02)
45 IO(Decode16, 0x28, 0x28, 0x01, 0x02)
46 IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
47 IO(Decode16, 0x30, 0x30, 0x01, 0x02)
48 IO(Decode16, 0x34, 0x34, 0x01, 0x02)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Dsbsysmem.h84 #define SR_COREINFO 0x00
85 #define SR_BWALLOC 0x04
86 #define SR_BISTSTAT 0x0c
87 #define SR_BANKINDEX 0x10
88 #define SR_BANKSTBYCTL 0x14
89 #define SR_PWRCTL 0x1e8
92 #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */
95 #define SRCI_PT_OCP_OCP 0
102 #define SRCI_LSS_MASK 0x00f00000
104 #define SRCI_LRS_MASK 0x0f000000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Dsbsysmem.h83 #define SR_COREINFO 0x00
84 #define SR_BWALLOC 0x04
85 #define SR_BISTSTAT 0x0c
86 #define SR_BANKINDEX 0x10
87 #define SR_BANKSTBYCTL 0x14
88 #define SR_PWRCTL 0x1e8
91 #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */
94 #define SRCI_PT_OCP_OCP 0
101 #define SRCI_LSS_MASK 0x00f00000
103 #define SRCI_LRS_MASK 0x0f000000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Dsbsysmem.h84 #define SR_COREINFO 0x00
85 #define SR_BWALLOC 0x04
86 #define SR_BISTSTAT 0x0c
87 #define SR_BANKINDEX 0x10
88 #define SR_BANKSTBYCTL 0x14
89 #define SR_PWRCTL 0x1e8
92 #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */
95 #define SRCI_PT_OCP_OCP 0
102 #define SRCI_LSS_MASK 0x00f00000
104 #define SRCI_LRS_MASK 0x0f000000
[all …]

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