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12

/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dmpc8349_pci.h5 #define M8265_PCIBR0 0x101ac
6 #define M8265_PCIBR1 0x101b0
7 #define M8265_PCIMSK0 0x101c4
8 #define M8265_PCIMSK1 0x101c8
12 #define PCIBR_ENABLE 0x00000001
16 #define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
17 #define PCIMSK_64KB 0xFFFF0000
18 #define PCIMSK_128KB 0xFFFE0000
19 #define PCIMSK_256KB 0xFFFC0000
20 #define PCIMSK_512KB 0xFFF80000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml38 "^emc-timings-[0-9]+$":
48 "^timing-[0-9]+$":
79 minimum: 0
142 minimum: 0
340 reg = <0x70019000 0x1000>;
352 reg = <0x7001b000 0x1000>;
358 emc-timings-0 {
361 timing-0 {
364 nvidia,emc-auto-cal-config = <0xa1430000>;
365 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_ifc.h18 #define FSL_IFC_V1_1_0 0x01010000
19 #define FSL_IFC_V2_0_0 0x02000000
39 #define CSPR_BA 0xFFFF0000
41 #define CSPR_PORT_SIZE 0x00000180
44 #define CSPR_PORT_SIZE_8 0x00000080
46 #define CSPR_PORT_SIZE_16 0x00000100
48 #define CSPR_PORT_SIZE_32 0x00000180
50 #define CSPR_WP 0x00000040
53 #define CSPR_MSEL 0x00000006
56 #define CSPR_MSEL_NOR 0x00000000
[all …]
H A Dmpc83xx.h24 #define EXC_OFF_SYS_RESET 0x0100
32 #define CONFIG_DEFAULT_IMMR 0xFF400000
35 #define IMMRBAR 0x0000
36 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
43 #define LBLAWBAR0 0x0020
44 #define LBLAWAR0 0x0024
45 #define LBLAWBAR1 0x0028
46 #define LBLAWAR1 0x002C
47 #define LBLAWBAR2 0x0030
48 #define LBLAWAR2 0x0034
[all …]
/OK3568_Linux_fs/kernel/drivers/ide/
H A Dit8172.c50 * it cannot be configured for PIO mode 0. This table sets these in it8172_set_pio_mode()
53 static const u8 timings[] = { 0x3f, 0x3c, 0x1b, 0x12, 0x0a }; in it8172_set_pio_mode()
55 pci_read_config_word(dev, 0x40, &drive_enables); in it8172_set_pio_mode()
56 pci_read_config_dword(dev, 0x44, &drive_timing); in it8172_set_pio_mode()
59 * Enable port 0x44. The IT8172 spec is confused; it calls in it8172_set_pio_mode()
63 drive_enables |= 0x4000; in it8172_set_pio_mode()
65 drive_enables &= drive->dn ? 0xc006 : 0xc060; in it8172_set_pio_mode()
68 drive_enables |= 0x0004 << (drive->dn * 4); in it8172_set_pio_mode()
71 drive_enables |= 0x0002 << (drive->dn * 4); in it8172_set_pio_mode()
73 drive_timing &= drive->dn ? 0x00003f00 : 0x000fc000; in it8172_set_pio_mode()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192c.c37 .reg_0e00 = 0x07090c0c,
38 .reg_0e04 = 0x01020405,
39 .reg_0e08 = 0x00000000,
40 .reg_086c = 0x00000000,
42 .reg_0e10 = 0x0b0c0c0e,
43 .reg_0e14 = 0x01030506,
44 .reg_0e18 = 0x0b0c0d0e,
45 .reg_0e1c = 0x01030509,
47 .reg_0830 = 0x07090c0c,
48 .reg_0834 = 0x01020405,
[all …]
H A Drtl8xxxu_8723a.c36 .reg_0e00 = 0x0a0c0c0c,
37 .reg_0e04 = 0x02040608,
38 .reg_0e08 = 0x00000000,
39 .reg_086c = 0x00000000,
41 .reg_0e10 = 0x0a0c0d0e,
42 .reg_0e14 = 0x02040608,
43 .reg_0e18 = 0x0a0c0d0e,
44 .reg_0e1c = 0x02040608,
46 .reg_0830 = 0x0a0c0c0c,
47 .reg_0834 = 0x02040608,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10005388,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/OK3568_Linux_fs/u-boot/board/engicam/common/
H A Dspl.c49 return 0; in spl_start_uboot()
56 * 0x30 == 40 Ohm
57 * 0x28 == 48 Ohm
59 #define IMX6DQ_DRIVE_STRENGTH 0x30
60 #define IMX6SDL_DRIVE_STRENGTH 0x28
87 .dram_sdba2 = 0x00000000,
103 .grp_ddrmode_ctl = 0x00020000,
104 .grp_ddrpke = 0x00000000,
105 .grp_ddrmode = 0x00020000,
107 .grp_ddr_type = 0x000c0000,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/ice/
H A Dice_hw_autogen.h9 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
11 #define QTX_COMM_HEAD_HEAD_S 0
12 #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
13 #define PF_FW_ARQBAH 0x00080180
14 #define PF_FW_ARQBAL 0x00080080
15 #define PF_FW_ARQH 0x00080380
16 #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
17 #define PF_FW_ARQLEN 0x00080280
18 #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/thermal/qcom/
H A Dtsens-v0_1.c10 #define SROT_CTRL_OFF 0x0000
13 #define TM_INT_EN_OFF 0x0000
14 #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15 #define TM_Sn_STATUS_OFF 0x0030
16 #define TM_TRDY_OFF 0x005c
19 #define MSM8916_BASE0_MASK 0x0000007f
20 #define MSM8916_BASE1_MASK 0xfe000000
21 #define MSM8916_BASE0_SHIFT 0
24 #define MSM8916_S0_P1_MASK 0x00000f80
25 #define MSM8916_S1_P1_MASK 0x003e0000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/adreno/
H A Da6xx.xml.h52 TILE6_LINEAR = 0,
182 DEPTH6_NONE = 0,
281 PERF_CP_ALWAYS_COUNT = 0,
334 PERF_RBBM_ALWAYS_COUNT = 0,
351 PERF_PC_BUSY_CYCLES = 0,
396 PERF_VFD_BUSY_CYCLES = 0,
422 PERF_HLSQ_BUSY_CYCLES = 0,
446 PERF_VPC_BUSY_CYCLES = 0,
477 PERF_TSE_BUSY_CYCLES = 0,
500 PERF_RAS_BUSY_CYCLES = 0,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/sun/
H A Dsunhme.h15 #define GREG_SWRESET 0x000UL /* Software Reset */
16 #define GREG_CFG 0x004UL /* Config Register */
17 #define GREG_STAT 0x100UL /* Status */
18 #define GREG_IMASK 0x104UL /* Interrupt Mask */
19 #define GREG_REG_SIZE 0x108UL
22 #define GREG_RESET_ETX 0x01
23 #define GREG_RESET_ERX 0x02
24 #define GREG_RESET_ALL 0x03
27 #define GREG_CFG_BURSTMSK 0x03
28 #define GREG_CFG_BURST16 0x00
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/halrf/rtl8822c/
H A Dhalrf_tssi_8822c.c48 for (i = 0; i < reg_num; i++) { in _backup_bb_registers_8822c()
51 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", in _backup_bb_registers_8822c()
66 for (i = 0; i < reg_num; i++) { in _reload_bb_registers_8822c()
68 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", in _reload_bb_registers_8822c()
78 u8 tssi_rate = 0; in _halrf_driver_rate_to_tssi_rate_8822c()
83 tssi_rate = 0; in _halrf_driver_rate_to_tssi_rate_8822c()
118 u8 driver_rate = 0; in _halrf_tssi_rate_to_driver_rate_8822c()
122 if (rate == 0) in _halrf_tssi_rate_to_driver_rate_8822c()
158 #if 0 in _halrf_calculate_txagc_codeword_8822c()
165 for (i = 0; i < TSSI_CODE_NUM; i++) { in _halrf_calculate_txagc_codeword_8822c()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv40.c31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
35 * opcode 0x60000d is called before resuming normal operation.
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath5k/
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath10k/
H A Drx_desc.h13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
57 * 0. The PPDU start status will only be valid when this bit
66 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
213 * ring 0. Field is filled in by the RX_DMA.
229 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
242 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
243 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
244 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
246 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
254 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
[all …]

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