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/OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/
H A Dsoc.h19 * the synchronous boot mode is selected. When ASDO is "0" (i.e
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
34 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
35 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
36 #define EP93XX_CS1_PHYS_BASE 0x10000000
37 #define EP93XX_CS2_PHYS_BASE 0x20000000
38 #define EP93XX_CS3_PHYS_BASE 0x30000000
39 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/OK3568_Linux_fs/kernel/arch/x86/include/asm/e820/
H A Dtypes.h37 E820_TYPE_SOFT_RESERVED = 0xefffffff,
102 #define ISA_START_ADDRESS 0x000a0000
103 #define ISA_END_ADDRESS 0x00100000
105 #define BIOS_BEGIN 0x000a0000
106 #define BIOS_END 0x00100000
108 #define HIGH_MEMORY 0x00100000
110 #define BIOS_ROM_BASE 0xffe00000
111 #define BIOS_ROM_END 0xffffffff
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm958522er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525xmc.dts48 reg = <0x60000000 0x40000000>;
78 reg = <0x4c>;
83 reg = <0x52>;
89 reg = <0x68>;
94 nand@0 {
96 reg = <0>;
107 partition@0 {
109 reg = <0x00000000 0x00200000>;
114 reg = <0x00200000 0x00400000>;
118 reg = <0x00600000 0x00a00000>;
[all …]
H A Dbcm988312hr.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958623hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958622hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625hr.dts48 reg = <0x60000000 0x20000000>;
93 nand@0 {
95 reg = <0>;
106 partition@0 {
108 reg = <0x00000000 0x00200000>;
113 reg = <0x00200000 0x00400000>;
117 reg = <0x00600000 0x00a00000>;
121 reg = <0x01000000 0x03000000>;
125 reg = <0x04000000 0x3c000000>;
144 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625k.dts47 reg = <0x60000000 0x80000000>;
72 nand@0 {
74 reg = <0>;
85 partition@0 {
87 reg = <0x00000000 0x00200000>;
92 reg = <0x00200000 0x00400000>;
96 reg = <0x00600000 0x00a00000>;
100 reg = <0x01000000 0x03000000>;
104 reg = <0x04000000 0x3c000000>;
127 pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;
[all …]
H A Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
H A Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-svk.dts50 bootargs = "earlycon=uart8250,mmio32,0x66130000";
55 reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
110 slic@0 {
112 reg = <0>;
116 pl022,hierarchy = <0>;
117 pl022,interface = <0>;
118 pl022,slave-tx-disable = <0>;
119 pl022,com-mode = <0>;
123 pl022,wait-state = <0>;
124 pl022,duplex = <0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
89 #address-cells = <0x1>;
90 #size-cells = <0x0>;
92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
95 interrupt-parent = <0x1c>;
107 m25p80@0 {
108 #size-cells = <0x2>;
109 #address-cells = <0x2>;
111 reg = <0x0>;
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dsh7757lcr.h16 #define CONFIG_SYS_TEXT_BASE 0x8ef80000
22 #define SH7757LCR_SDRAM_BASE (0x80000000)
24 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
46 #define CONFIG_SYS_MONITOR_BASE 0x00000000
53 #define CONFIG_SH_ETHER_USE_PORT 0
60 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
70 #define CONFIG_SH_SPI_BASE 0xfe002000
74 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
78 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
79 #define SH7757LCR_GRA_OFFSET 0x1f000000
[all …]
H A Ddevkit3250.h31 #define CONFIG_SYS_TEXT_BASE 0x83F00000
75 #define CONFIG_PHY_ADDR 0x1F
106 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
114 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
134 #define CONFIG_ENV_OFFSET 0x000A0000
145 "autoload=no\0" \
146 "ethaddr=00:01:90:00:C0:81\0" \
147 "dtbaddr=0x81000000\0" \
148 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
149 "tftpdir=vladimir/oe/devkit3250\0" \
[all …]
/OK3568_Linux_fs/buildroot/support/testing/tests/package/br2-external/openjdk/package/openjdk-jni-test/
H A DJniTest.java36 var expectedVersion = 0x000A0000; in main()
41 String.format("0x%08X", actualVersion), in main()
42 String.format("0x%08X", expectedVersion)); in main()
91 public static int exitCode = 0;
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/OK3568_Linux_fs/kernel/arch/x86/include/uapi/asm/
H A De820.h4 #define E820MAP 0x2d0 /* our map */
29 #define E820NR 0x1e8 /* # entries in E820MAP */
70 #define ISA_START_ADDRESS 0xa0000
71 #define ISA_END_ADDRESS 0x100000
73 #define BIOS_BEGIN 0x000a0000
74 #define BIOS_END 0x00100000
76 #define BIOS_ROM_BASE 0xffe00000
77 #define BIOS_ROM_END 0xffffffff
/OK3568_Linux_fs/kernel/arch/arm/mach-footbridge/
H A Debsa285.c22 #define XBUS_AMBER_L BIT(0)
84 for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) { in ebsa285_leds_init()
97 if (led_classdev_register(NULL, &led->cdev) < 0) { in ebsa285_leds_init()
103 return 0; in ebsa285_leds_init()
115 .atag_offset = 0x100,
116 .video_start = 0x000a0000,
117 .video_end = 0x000bffff,
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/fsp/
H A Dfsp_fv.h12 #define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
13 #define EFI_FV_FILE_ATTR_FIXED 0x00000100
14 #define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
17 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
18 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
19 #define EFI_FVB2_READ_STATUS 0x00000004
20 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
21 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
22 #define EFI_FVB2_WRITE_STATUS 0x00000020
23 #define EFI_FVB2_LOCK_CAP 0x00000040
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx5/
H A Dlowlevel_init.S18 mrc 15, 0, r1, c1, c0, 1
20 mcr 15, 0, r1, c1, c0, 1
28 mrc 15, 0, r0, c1, c0, 1
29 bic r0, r0, #0x2
30 mcr 15, 0, r0, c1, c0, 1
33 ldr r0, =0xC0 | /* tag RAM */ \
34 0x4 | /* data RAM */ \
41 cmp r3, #0x10
50 mrc 15, 0, r0, c1, c0, 1
52 mcr 15, 0, r0, c1, c0, 1
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]

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