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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Domap4460.dtsi15 cpu0: cpu@0 {
42 reg = <0x4a002260 0x4
43 0x4a00232C 0x4
44 0x4a002378 0x18>;
46 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
49 #thermal-sensor-cells = <0>;
55 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
56 <0x4A002268 0x4>;
62 1025000 0 0 0 0 0
63 1200000 0 0 0 0 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43legacy/
H A Ddma.h24 #define B43legacy_DMA32_TXCTL 0x00
25 #define B43legacy_DMA32_TXENABLE 0x00000001
26 #define B43legacy_DMA32_TXSUSPEND 0x00000002
27 #define B43legacy_DMA32_TXLOOPBACK 0x00000004
28 #define B43legacy_DMA32_TXFLUSH 0x00000010
29 #define B43legacy_DMA32_TXADDREXT_MASK 0x00030000
31 #define B43legacy_DMA32_TXRING 0x04
32 #define B43legacy_DMA32_TXINDEX 0x08
33 #define B43legacy_DMA32_TXSTATUS 0x0C
34 #define B43legacy_DMA32_TXDPTR 0x00000FFF
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv40.c37 u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); in nv40_mpeg_mthd_dma()
40 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); in nv40_mpeg_mthd_dma()
44 if (!(dma0 & 0x00002000)) { in nv40_mpeg_mthd_dma()
50 if (mthd == 0x0190) { in nv40_mpeg_mthd_dma()
52 nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000)); in nv40_mpeg_mthd_dma()
53 nvkm_wr32(device, 0x00b334, base); in nv40_mpeg_mthd_dma()
54 nvkm_wr32(device, 0x00b324, size); in nv40_mpeg_mthd_dma()
56 if (mthd == 0x01a0) { in nv40_mpeg_mthd_dma()
58 nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); in nv40_mpeg_mthd_dma()
59 nvkm_wr32(device, 0x00b360, base); in nv40_mpeg_mthd_dma()
[all …]
H A Dnv31.c44 if (ret == 0) { in nv31_mpeg_object_bind()
46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv31_mpeg_object_bind()
47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv31_mpeg_object_bind()
48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv31_mpeg_object_bind()
49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv31_mpeg_object_bind()
103 ret = 0; in nv31_mpeg_chan_new()
119 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile()
120 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile()
121 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile()
130 u32 dma0 = nvkm_rd32(device, 0x700000 + inst); in nv31_mpeg_mthd_dma()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/via/
H A Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dpiocnv50.c38 nvkm_mask(device, 0x610200 + (ctrl * 0x10), 0x00000001, 0x00000000); in nv50_disp_pioc_fini()
40 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) in nv50_disp_pioc_fini()
42 ) < 0) { in nv50_disp_pioc_fini()
44 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_pioc_fini()
57 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00002000); in nv50_disp_pioc_init()
59 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000)) in nv50_disp_pioc_init()
61 ) < 0) { in nv50_disp_pioc_init()
63 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_pioc_init()
67 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00000001); in nv50_disp_pioc_init()
69 u32 tmp = nvkm_rd32(device, 0x610200 + (ctrl * 0x10)); in nv50_disp_pioc_init()
[all …]
H A Dpiocgf119.c38 nvkm_mask(device, 0x610490 + (ctrl * 0x10), 0x00000001, 0x00000000); in gf119_disp_pioc_fini()
40 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000)) in gf119_disp_pioc_fini()
42 ) < 0) { in gf119_disp_pioc_fini()
44 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_fini()
58 nvkm_wr32(device, 0x610490 + (ctrl * 0x10), 0x00000001); in gf119_disp_pioc_init()
60 u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10)); in gf119_disp_pioc_init()
61 if ((tmp & 0x00030000) == 0x00010000) in gf119_disp_pioc_init()
63 ) < 0) { in gf119_disp_pioc_init()
65 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_init()
69 return 0; in gf119_disp_pioc_init()
/OK3568_Linux_fs/kernel/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_a38x_mc_static.h17 {0x1400, 0x7b00cc30, 0xffffffff},
18 {0x1404, 0x36301820, 0xffffffff},
19 {0x1408, 0x5415baab, 0xffffffff},
20 {0x140c, 0x38411def, 0xffffffff},
21 {0x1410, 0x18300000, 0xffffffff},
22 {0x1414, 0x00000700, 0xffffffff},
23 {0x1424, 0x0060f3ff, 0xffffffff},
24 {0x1428, 0x0011a940, 0xffffffff},
25 {0x142c, 0x28c5134, 0xffffffff},
26 {0x1474, 0x00000000, 0xffffffff},
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/
H A Dsoc.h19 * the synchronous boot mode is selected. When ASDO is "0" (i.e
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
34 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
35 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
36 #define EP93XX_CS1_PHYS_BASE 0x10000000
37 #define EP93XX_CS2_PHYS_BASE 0x20000000
38 #define EP93XX_CS3_PHYS_BASE 0x30000000
39 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dtable.c9 0x024, 0x0011800d,
10 0x028, 0x00ffdb83,
11 0x014, 0x088ba955,
12 0x010, 0x49022b03,
13 0x800, 0x80040002,
14 0x804, 0x00000003,
15 0x808, 0x0000fc00,
16 0x80c, 0x0000000a,
17 0x810, 0x80706388,
18 0x814, 0x020c3d10,
[all …]
/OK3568_Linux_fs/kernel/sound/soc/fsl/
H A Dfsl_dma.h10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Dbcm-sf2-eth-gmac.h16 #define GMAC0_REG_BASE 0x18042000
18 #define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
19 #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
20 #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
23 #define GMAC_DMA_PTR_OFFSET 0x04
24 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08
25 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
26 #define GMAC_DMA_STATUS0_OFFSET 0x10
27 #define GMAC_DMA_STATUS1_OFFSET 0x14
29 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h17 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
18 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
19 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
20 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
21 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
22 #define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
23 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
24 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
25 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
26 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
[all …]
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dm5272.h21 #define GPIO_PACNT_PA15MSK (0xC0000000)
22 #define GPIO_PACNT_DGNT1 (0x40000000)
23 #define GPIO_PACNT_PA14MSK (0x30000000)
24 #define GPIO_PACNT_DREQ1 (0x10000000)
25 #define GPIO_PACNT_PA13MSK (0x0C000000)
26 #define GPIO_PACNT_DFSC3 (0x04000000)
27 #define GPIO_PACNT_PA12MSK (0x03000000)
28 #define GPIO_PACNT_DFSC2 (0x01000000)
29 #define GPIO_PACNT_PA11MSK (0x00C00000)
30 #define GPIO_PACNT_QSPI_CS1 (0x00800000)
[all …]
/OK3568_Linux_fs/kernel/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-4G-1600.dtsi9 0x2
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi9 0x2
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-ddr3-1866.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]

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