Home
last modified time | relevance | path

Searched +full:0 +full:x00010001 (Results 1 – 25 of 146) sorted by relevance

123456

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dhdmigt215.c31 const u32 ctrl = 0x40000000 * enable | in gt215_hdmi_ctrl()
32 0x1f000000 /* ??? */ | in gt215_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in gt215_hdmi_ctrl()
43 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000); in gt215_hdmi_ctrl()
44 nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
45 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
46 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
51 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
53 nvkm_wr32(device, 0x61c528 + soff, avi_infoframe.header); in gt215_hdmi_ctrl()
54 nvkm_wr32(device, 0x61c52c + soff, avi_infoframe.subpack0_low); in gt215_hdmi_ctrl()
[all …]
H A Dhdmig84.c31 const u32 ctrl = 0x40000000 * enable | in g84_hdmi_ctrl()
32 0x1f000000 /* ??? */ | in g84_hdmi_ctrl()
35 const u32 hoff = head * 0x800; in g84_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in g84_hdmi_ctrl()
43 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); in g84_hdmi_ctrl()
44 nvkm_mask(device, 0x61653c + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
45 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
46 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
51 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
53 nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header); in g84_hdmi_ctrl()
[all …]
/OK3568_Linux_fs/external/rkwifibt/firmware/broadcom/AP6203BM/wifi/
H A Dnvram_ap6201bm.txt5 etmode=0x11
7 bphyscale=0x28
8 boardflags3=0x40000101
9 vendid=0x14e4
10 devid=0xA804
11 manfid=0x2d0
12 prodid=0x052e
15 boardtype=0x080e
16 boardrev=0x1103
17 lpflags=0x00000020
[all …]
H A Dnvram_ap6203bm.txt1 #AP6203BM_NVRAM_V1.0_20200305
5 etmode=0x11
7 bphyscale=0x28
8 boardflags3=0x40000101
9 vendid=0x14e4
10 devid=0xA804
11 manfid=0x2d0
12 prodid=0x052e
15 boardtype=0x080e
16 boardrev=0x1103
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr600_mt47h32m16_37e_166_cl4_sync.c13 0x03030301,
14 0x03030303,
15 0x01000000,
16 0x00000101,
17 0x00000001,
18 0x01000000,
19 0x00010001,
20 0x00000100,
21 0x00010001,
22 0x00000003,
[all …]
H A Dspr600_mt47h128m8_3_266_cl5_async.c13 0x00000001,
14 0x00000000,
15 0x01000000,
16 0x00000101,
17 0x00000001,
18 0x01000000,
19 0x00010001,
20 0x00000100,
21 0x00010001,
22 0x00000003,
[all …]
H A Dspr600_mt47h64m16_3_333_cl5_psync.c14 0x00000001,
15 0x00000000,
17 0x02020201,
18 0x02020202,
20 0x01000000,
21 0x00000101,
22 0x00000101,
23 0x01000000,
24 0x00010001,
25 0x00000100,
[all …]
H A Dspr600_mt47h32m16_333_cl5_psync.c14 0x00000001,
15 0x00000000,
17 0x02020201,
18 0x02020202,
20 0x01000000,
21 0x00000101,
22 0x00000101,
23 0x01000000,
24 0x00010001,
25 0x00000100,
[all …]
/OK3568_Linux_fs/external/rkwifibt/firmware/infineon/CYW43012/
H A Dcyw43012.txt3 ##SSID: 0x085a
4 ##macmid: 0x02bb
14 etmode=0x11
16 bphyscale=0x20
17 boardflags3=0x4000C101
18 vendid=0x14e4
19 devid=0xA804
20 manfid=0x2d0
21 prodid=0x052e
24 boardtype=0x085c
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
31 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
40 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
72 #define MSGDMA_DESC_TX_STRIDE (0x00010001)
73 #define MSGDMA_DESC_RX_STRIDE (0x00010001)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
92 #define MSGDMA_CSR_STAT_BUSY BIT(0)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h109 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
110 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
115 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
116 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
117 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
118 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
119 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
120 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
121 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
122 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Daltera_tse.h17 #define ALT_SGDMA 0
34 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
122 #define MSGDMA_DESC_TX_STRIDE 0x00010001
123 #define MSGDMA_DESC_RX_STRIDE 0x00010001
130 u32 resp_fill_level; /* bit 15:0 */
136 #define MSGDMA_CSR_STAT_BUSY BIT(0)
138 #define MSGDMA_CSR_STAT_MASK 0x3FF
150 #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
181 u32 reserved1[0x29];
187 u32 reserved2[0x44];
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c74 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
75 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
H A Dctxgf119.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/OK3568_Linux_fs/u-boot/board/udoo/
H A Dudoo_spl.c31 * 0x30 == 40 Ohm
32 * 0x28 == 48 Ohm
34 #define IMX6DQ_DRIVE_STRENGTH 0x30
35 #define IMX6SDL_DRIVE_STRENGTH 0x28
46 .dram_sdba2 = 0x00000000,
69 .grp_ddr_type = 0x000c0000,
70 .grp_ddrmode_ctl = 0x00020000,
71 .grp_ddrpke = 0x00000000,
74 .grp_ddrmode = 0x00020000,
94 .dram_sdba2 = 0x00000000,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi9 0x2
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-lpddr4-100.dtsi6 0x2
7 0xa
8 0x3
9 0x2
10 0x1
11 0x0
12 0xf
13 0xf
14 0
15 0
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]
/OK3568_Linux_fs/kernel/sound/soc/amd/renoir/
H A Drn_acp3x.h11 #define ACP_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_REG_START 0x1240000
13 #define ACP_REG_END 0x1250200
15 #define ACP_DEVICE_ID 0x15E2
16 #define ACP_POWER_ON 0x00
17 #define ACP_POWER_ON_IN_PROGRESS 0x01
18 #define ACP_POWER_OFF 0x02
19 #define ACP_POWER_OFF_IN_PROGRESS 0x03
20 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
22 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
[all …]
/OK3568_Linux_fs/kernel/arch/alpha/include/asm/
H A Djensen.h34 #define EISA_INTA (IDENT_ADDR + 0x100000000UL)
39 #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL)
40 #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL)
45 #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL)
50 #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL)
55 #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL)
60 #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL)
65 #define EISA_MEM (IDENT_ADDR + 0x200000000UL)
70 #define EISA_IO (IDENT_ADDR + 0x300000000UL)
84 * hae needs to be set to 0).
[all …]
/OK3568_Linux_fs/buildroot/board/technexion/imx6ulpico/rootfs_overlay/lib/firmware/brcm/
H A Dbrcmfmac4339-sdio.txt3 boardrev=0x1100
4 boardtype=0x06c9
5 boardflags=0x10081401
6 boardflags2=0x00000000
7 boardflags3=0x08001188
10 ccode=0
11 regrev=0
12 antswitch=0
15 tworangetssi2g=0
16 tworangetssi5g=0
[all …]

123456