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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgk104.c36 { 0x100d10, 1, 0x0000c244 },
37 { 0x100d30, 1, 0x0000c242 },
38 { 0x100d3c, 1, 0x00000242 },
39 { 0x100d48, 1, 0x00000242 },
40 { 0x100d1c, 1, 0x00000042 },
46 { 0x100c98, 1, 0x00000242 },
52 { 0x10f000, 1, 0x00000042 },
53 { 0x17e030, 1, 0x00000044 },
54 { 0x17e040, 1, 0x00000044 },
60 { 0x17ea60, 4, 0x00000044 },
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/OK3568_Linux_fs/u-boot/board/compulab/cm_t43/
H A Dspl.c32 .emif_sdram_config_ext = 0x0143,
37 .sdram_config = 0x638413B2,
38 .ref_ctrl = 0x00000C30,
39 .sdram_tim1 = 0xEAAAD4DB,
40 .sdram_tim2 = 0x266B7FDA,
41 .sdram_tim3 = 0x107F8678,
42 .read_idle_ctrl = 0x00050000,
43 .zq_config = 0x50074BE4,
44 .temp_alert_config = 0x0,
45 .emif_ddr_phy_ctlr_1 = 0x0E004008,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dp/
H A Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp1/
H A Dregs.h40 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
41 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
44 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
47 #define GRF_VI_CON0 0x430
48 #define ISP_CIF_DATA_WIDTH_MASK 0x60006000
49 #define ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
54 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
55 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
74 #define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
77 #define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Dregs.h42 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
43 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
46 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
49 #define GRF_VI_CON0 0x430
50 #define ISP_CIF_DATA_WIDTH_MASK 0x60006000
51 #define ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
56 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
57 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
76 #define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
79 #define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar9330_1p2_initvals.h45 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
46 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
47 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
48 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
49 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
50 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
51 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
52 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
53 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
54 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
[all …]
H A Dar9330_1p1_initvals.h27 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
28 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
29 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
30 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
31 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
32 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
33 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
34 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
35 {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
36 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/
H A Ddsi.xml.h50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dmb862xx.h15 #define PCI_VENDOR_ID_FUJITSU 0x10CF
16 #define PCI_DEVICE_ID_CORAL_P 0x2019
17 #define PCI_DEVICE_ID_CORAL_PA 0x201E
19 #define MB862XX_TYPE_LIME 0x1
21 #define GC_HOST_BASE 0x01fc0000
22 #define GC_DISP_BASE 0x01fd0000
23 #define GC_DRAW_BASE 0x01ff0000
26 #define GC_SRST 0x0000002c
27 #define GC_CCF 0x00000038
28 #define GC_CID 0x000000f0
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl006c.h27 #define NV06C_PUT (0x00000040)
29 #define NV06C_GET (0x00000044)
37 #define NV06C_OPCODE_METHOD (0x00000000)
38 #define NV06C_OPCODE_NONINC_METHOD (0x00000002)
41 #define NV06C_DATA 31:0
44 #define NV06C_OPCODE_JUMP (0x00000001)
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/hal/phydm/rtl8188f/
H A Dhalhwimg8188f_mac.c30 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ in check_positive()
41 u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; in check_positive()
44 (dm->support_interface & 0xF0) << 16 | in check_positive()
47 (dm->support_interface & 0x0F) << 8 | in check_positive()
50 u32 driver2 = (dm->type_glna & 0xFF) << 0 | in check_positive()
51 (dm->type_gpa & 0xFF) << 8 | in check_positive()
52 (dm->type_alna & 0xFF) << 16 | in check_positive()
53 (dm->type_apa & 0xFF) << 24; in check_positive()
55 u32 driver3 = 0; in check_positive()
57 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | in check_positive()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/hal/phydm/rtl8188f/
H A Dhalhwimg8188f_mac.c31 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ in check_positive()
42 u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; in check_positive()
45 (dm->support_interface & 0xF0) << 16 | in check_positive()
48 (dm->support_interface & 0x0F) << 8 | in check_positive()
51 u32 driver2 = (dm->type_glna & 0xFF) << 0 | in check_positive()
52 (dm->type_gpa & 0xFF) << 8 | in check_positive()
53 (dm->type_alna & 0xFF) << 16 | in check_positive()
54 (dm->type_apa & 0xFF) << 24; in check_positive()
56 u32 driver3 = 0; in check_positive()
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | in check_positive()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/hal/phydm/rtl8188f/
H A Dhalhwimg8188f_mac.c30 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ in check_positive()
41 u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; in check_positive()
44 (dm->support_interface & 0xF0) << 16 | in check_positive()
47 (dm->support_interface & 0x0F) << 8 | in check_positive()
50 u32 driver2 = (dm->type_glna & 0xFF) << 0 | in check_positive()
51 (dm->type_gpa & 0xFF) << 8 | in check_positive()
52 (dm->type_alna & 0xFF) << 16 | in check_positive()
53 (dm->type_apa & 0xFF) << 24; in check_positive()
55 u32 driver3 = 0; in check_positive()
57 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | in check_positive()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/hal/phydm/rtl8188f/
H A Dhalhwimg8188f_mac.c31 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ in check_positive()
42 u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; in check_positive()
45 (dm->support_interface & 0xF0) << 16 | in check_positive()
48 (dm->support_interface & 0x0F) << 8 | in check_positive()
51 u32 driver2 = (dm->type_glna & 0xFF) << 0 | in check_positive()
52 (dm->type_gpa & 0xFF) << 8 | in check_positive()
53 (dm->type_alna & 0xFF) << 16 | in check_positive()
54 (dm->type_apa & 0xFF) << 24; in check_positive()
56 u32 driver3 = 0; in check_positive()
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | in check_positive()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/tegra/
H A Dfalcon.h11 #define FALCON_UCLASS_METHOD_OFFSET 0x00000040
13 #define FALCON_UCLASS_METHOD_DATA 0x00000044
15 #define FALCON_IRQMSET 0x00001010
21 #define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8)
23 #define FALCON_IRQDEST 0x0000101c
28 #define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8)
30 #define FALCON_ITFEN 0x00001048
31 #define FALCON_ITFEN_CTXEN (1 << 0)
34 #define FALCON_IDLESTATE 0x0000104c
36 #define FALCON_CPUCTL 0x00001100
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-regs.h14 #define UMC_CPURST 0x00000700
15 #define UMC_IDSRST 0x0000070C
16 #define UMC_IXMRST 0x00000714
17 #define UMC_HDMRST 0x00000718
18 #define UMC_MDMRST 0x0000071C
19 #define UMC_HDDRST 0x00000720
20 #define UMC_MDDRST 0x00000724
21 #define UMC_SIORST 0x00000728
22 #define UMC_GIORST 0x0000072C
23 #define UMC_HD2RST 0x00000734
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/ssv6xxx/include/
H A Dssv6200_configuration.h18 {0xce0071bc, 0x565B565B},
19 {0xce000008, 0x0000006a},
20 {0xce00000c, 0x00000064},
21 {0xce000010, 0x00007FFF},
22 {0xce000014, 0x00000003},
23 {0xce000018, 0x0055003C},
24 {0xce00001c, 0x00000064},
25 {0xce000020, 0x20000000},
26 {0xce00002c, 0x00000000},
27 {0xce000030, 0x80046072},
[all …]
/OK3568_Linux_fs/u-boot/board/maxbcm/
H A Dmaxbcm.c20 #define DEV_CS0_BASE 0xe0000000
21 #define DEV_CS1_BASE 0xe1000000
22 #define DEV_CS2_BASE 0xe2000000
23 #define DEV_CS3_BASE 0xe3000000
27 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
28 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
29 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
30 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
31 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
32 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]
/OK3568_Linux_fs/kernel/drivers/crypto/amcc/
H A Dcrypto4xx_reg_def.h15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
[all …]
/OK3568_Linux_fs/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg21 # Configure RGMII-0 interface pad voltage to 1.8V
22 DATA 0xFFD100e0 0x1B1B1B9B
25 DATA 0xFFD01400 0x43000C30 # DDR Configuration register
26 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
33 DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
34 # bit 4: 0=addr/cmd in smame cycle
35 # bit 5: 0=clk is driven during self refresh, we don't care for APX
36 # bit 6: 0=use recommended falling edge of clk for addr/cmd
37 # bit14: 0=input buffer always powered up
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
[all …]
/OK3568_Linux_fs/kernel/include/linux/mmc/
H A Dsh_mmcif.h33 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
38 #define MMCIF_CE_CMD_SET 0x00000000
39 #define MMCIF_CE_ARG 0x00000008
40 #define MMCIF_CE_ARG_CMD12 0x0000000C
41 #define MMCIF_CE_CMD_CTRL 0x00000010
42 #define MMCIF_CE_BLOCK_SET 0x00000014
43 #define MMCIF_CE_CLK_CTRL 0x00000018
44 #define MMCIF_CE_BUF_ACC 0x0000001C
45 #define MMCIF_CE_RESP3 0x00000020
46 #define MMCIF_CE_RESP2 0x00000024
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv50.c42 if (ret == 0) { in nv50_mpeg_cclass_bind()
44 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1); in nv50_mpeg_cclass_bind()
45 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c); in nv50_mpeg_cclass_bind()
65 u32 stat = nvkm_rd32(device, 0x00b100); in nv50_mpeg_intr()
66 u32 type = nvkm_rd32(device, 0x00b230); in nv50_mpeg_intr()
67 u32 mthd = nvkm_rd32(device, 0x00b234); in nv50_mpeg_intr()
68 u32 data = nvkm_rd32(device, 0x00b238); in nv50_mpeg_intr()
71 if (stat & 0x01000000) { in nv50_mpeg_intr()
73 if (type == 0x00000020 && mthd == 0x0000) { in nv50_mpeg_intr()
74 nvkm_wr32(device, 0x00b308, 0x00000100); in nv50_mpeg_intr()
[all …]

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