Home
last modified time | relevance | path

Searched +full:0 +full:x0000003f (Results 1 – 25 of 326) sorted by relevance

12345678910>>...14

/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/coldfire/
H A Dlcd.h15 u32 ssar; /* 0x00 Screen Start Address Register */
16 u32 sr; /* 0x04 LCD Size Register */
17 u32 vpw; /* 0x08 Virtual Page Width Register */
18 u32 cpr; /* 0x0C Cursor Position Register */
19 u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
20 u32 ccmr; /* 0x14 Color Cursor Mapping Register */
21 u32 pcr; /* 0x18 Panel Configuration Register */
22 u32 hcr; /* 0x1C Horizontal Configuration Register */
23 u32 vcr; /* 0x20 Vertical Configuration Register */
24 u32 por; /* 0x24 Panning Offset Register */
[all …]
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Drtc.h15 u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
16 u32 seconds; /* 0x04 Seconds Counter Register */
17 u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
18 u32 alrm_sec; /* 0x0C Seconds Alarm Register */
19 u32 cr; /* 0x10 Control Register */
20 u32 isr; /* 0x14 Interrupt Status Register */
21 u32 ier; /* 0x18 Interrupt Enable Register */
22 u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
23 u32 days; /* 0x20 Days Counter Register */
24 u32 alrm_day; /* 0x24 Days Alarm Register */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_arria10.h209 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
211 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
213 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
215 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
217 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
219 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
221 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
222 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
230 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
244 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
[all …]
H A Dclock_manager_arria10.h109 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
110 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
115 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
116 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
117 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
118 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
119 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
120 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
121 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
122 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/OK3568_Linux_fs/u-boot/board/kmc/kzm9g/
H A Dkzm9g.c17 #define CS0BCR_D (0x06C00400)
18 #define CS4BCR_D (0x16c90400)
19 #define CS0WCR_D (0x55062C42)
20 #define CS4WCR_D (0x1e071dc3)
25 #define VCLKCR1_D (0x27)
32 #define PORT32CR (0xE6051020)
33 #define PORT33CR (0xE6051021)
34 #define PORT34CR (0xE6051022)
35 #define PORT35CR (0xE6051023)
43 while (timeout > 0) { in cmp_loop()
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dpowernow-k8.h43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
/OK3568_Linux_fs/kernel/include/linux/ssb/
H A Dssb_driver_extif.h24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
/OK3568_Linux_fs/kernel/drivers/media/rc/img-ir/
H A Dimg-ir.h20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A Dgf100.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_ibus_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_ibus_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_ibus_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_ibus_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_ibus_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_ibus_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_ibus_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_ibus_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_ibus_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_ibus_intr()
[all …]
H A Dgk104.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); in gk104_ibus_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); in gk104_ibus_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); in gk104_ibus_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); in gk104_ibus_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); in gk104_ibus_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); in gk104_ibus_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); in gk104_ibus_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); in gk104_ibus_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); in gk104_ibus_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x120058); in gk104_ibus_intr()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_psd_8852b.c28 for (i = 0; i < reg_num; i++) { in _halrf_psd_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", in _halrf_psd_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _halrf_psd_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", in _halrf_psd_reload_bb_registers_8852b()
59 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, in halrf_psd_init_8852b()
60 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, in halrf_psd_init_8852b()
61 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, in halrf_psd_init_8852b()
62 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, in halrf_psd_init_8852b()
63 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, in halrf_psd_init_8852b()
64 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, in halrf_psd_init_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_psd_8852b.c28 for (i = 0; i < reg_num; i++) { in _halrf_psd_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", in _halrf_psd_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _halrf_psd_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", in _halrf_psd_reload_bb_registers_8852b()
59 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, in halrf_psd_init_8852b()
60 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, in halrf_psd_init_8852b()
61 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, in halrf_psd_init_8852b()
62 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, in halrf_psd_init_8852b()
63 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, in halrf_psd_init_8852b()
64 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, in halrf_psd_init_8852b()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/nohash/32/
H A Dmmu-44x.h10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
13 #define PPC44x_TLB_PAGEID 0
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/renesas/
H A Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dati_radeon_fb.h97 for (i=0; i < 2000000; i++) { in radeon_engine_flush()
109 for (i=0; i<2000000; i++) { in _radeon_fifo_wait()
110 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()
124 for (i=0; i<2000000; i++) { in _radeon_engine_idle()
125 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()
250 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); in __INPLL()
261 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); in __OUTPLL()
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/hal/phydm/halrf/
H A Dhalrf_kfree.c42 if ((data % 2) != 0) { /*odd->positive*/ in phydm_set_kfree_to_rf_8814a()
47 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0); in phydm_set_kfree_to_rf_8814a()
53 case 0: in phydm_set_kfree_to_rf_8814a()
54 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
55 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0); in phydm_set_kfree_to_rf_8814a()
56 cali_info->kfree_offset[e_rf_path] = 0; in phydm_set_kfree_to_rf_8814a()
60 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0); in phydm_set_kfree_to_rf_8814a()
61 cali_info->kfree_offset[e_rf_path] = 0; in phydm_set_kfree_to_rf_8814a()
64 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
74 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/hal/phydm/halrf/
H A Dhalrf_kfree.c43 if ((data % 2) != 0) { /*odd->positive*/ in phydm_set_kfree_to_rf_8814a()
48 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0); in phydm_set_kfree_to_rf_8814a()
54 case 0: in phydm_set_kfree_to_rf_8814a()
55 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
56 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0); in phydm_set_kfree_to_rf_8814a()
57 cali_info->kfree_offset[e_rf_path] = 0; in phydm_set_kfree_to_rf_8814a()
61 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0); in phydm_set_kfree_to_rf_8814a()
62 cali_info->kfree_offset[e_rf_path] = 0; in phydm_set_kfree_to_rf_8814a()
65 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
75 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-4G-1600.dtsi9 0x2
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-ddr3-1866.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]

12345678910>>...14