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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/sdram_inc/rk3308/
H A Dsdram-rk3308-ddr3-detect-589.inc2 0,
3 0,
4 0,
5 0,
7 .ddr_type = 0x3,
8 .chn_cnt = 0x0,
9 .rank = 0x1,
10 .cs0_row = 0x0,
11 .cs1_row = 0x0,
12 .bank = 0x3,
[all …]
/OK3568_Linux_fs/u-boot/board/boundary/nitrogen6x/
H A D800mhz_2x128mx16.cfg7 DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
8 DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
9 DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
10 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
11 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
12 DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
13 DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
14 DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
15 DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
16 DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/OK3568_Linux_fs/u-boot/board/toradex/colibri_imx6/
H A D800mhz_2x64mx16.cfg8 DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
9 DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
10 DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
11 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
12 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
13 DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
14 DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
15 DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
16 /* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
17 DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
[all …]
H A D800mhz_4x64mx16.cfg8 DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
9 DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
10 DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
11 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
12 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
13 DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
14 DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
15 DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
16 /* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
17 DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c36 #define MC_CG_ARB_FREQ_F0 0x0a
37 #define MC_CG_ARB_FREQ_F1 0x0b
38 #define MC_CG_ARB_FREQ_F2 0x0c
39 #define MC_CG_ARB_FREQ_F3 0x0d
41 #define MC_CG_SEQ_DRAMCONF_S0 0x05
42 #define MC_CG_SEQ_DRAMCONF_S1 0x06
43 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
44 #define MC_CG_SEQ_YCLK_RESUME 0x0a
46 #define SMC_RAM_END 0x8000
61 0x000008f8, 0x00000010, 0xffffffff,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/OK3568_Linux_fs/u-boot/board/tqc/tqma6/
H A Dtqma6s.cfg34 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
35 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
36 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
37 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
38 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
39 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
40 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
41 DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
42 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
43 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/asm/
H A Dptrace.h37 #define PTRACE_GETFDPIC_EXEC 0
44 #define USR26_MODE 0x00000000
45 #define FIQ26_MODE 0x00000001
46 #define IRQ26_MODE 0x00000002
47 #define SVC26_MODE 0x00000003
48 #define USR_MODE 0x00000010
49 #define SVC_MODE 0x00000013
50 #define FIQ_MODE 0x00000011
51 #define IRQ_MODE 0x00000012
52 #define MON_MODE 0x00000016
[all …]
/OK3568_Linux_fs/kernel/arch/arm/include/uapi/asm/
H A Dptrace.h37 #define PTRACE_GETFDPIC_EXEC 0
44 #define USR26_MODE 0x00000000
45 #define FIQ26_MODE 0x00000001
46 #define IRQ26_MODE 0x00000002
47 #define SVC26_MODE 0x00000003
50 * Use 0 here to get code right that creates a userspace
53 #define USR_MODE 0x00000000
54 #define SVC_MODE 0x00000000
56 #define USR_MODE 0x00000010
57 #define SVC_MODE 0x00000013
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/net/
H A Dpsock_lib.h31 * ether type 0x800 and in pair_udp_setfilter()
37 * jne #0x800, drop ; ETH_P_IP in pair_udp_setfilter()
48 * ret #0 in pair_udp_setfilter()
51 { 0x28, 0, 0, 0x0000000c }, in pair_udp_setfilter()
52 { 0x15, 0, 8, 0x00000800 }, in pair_udp_setfilter()
53 { 0x30, 0, 0, 0x00000017 }, in pair_udp_setfilter()
54 { 0x15, 0, 6, 0x00000011 }, in pair_udp_setfilter()
55 { 0x80, 0, 0, 0000000000 }, in pair_udp_setfilter()
56 { 0x35, 0, 4, 0x00000064 }, in pair_udp_setfilter()
57 { 0x30, 0, 0, 0x00000050 }, in pair_udp_setfilter()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/halrf/rtl8822c/
H A Dhalhwimg8822c_rf.c29 #define ODM_WIN 0x08
44 #define CUT_DONT_CARE 0xf
45 #define RFE_DONT_CARE 0xff
46 #define PARA_IF 0x8
47 #define PARA_ELSE_IF 0x9
48 #define PARA_ELSE 0xa
49 #define PARA_END 0xb
50 #define PARA_CHK 0x4
61 u32 cut_para = 0, rfe_para = 0; in halbb_sel_headline()
62 u32 compare_target = 0; in halbb_sel_headline()
[all …]
/OK3568_Linux_fs/u-boot/board/barco/titanium/
H A Dimximage.cfg44 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
45 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
46 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
47 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
48 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
49 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
50 DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
51 DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
53 DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
54 DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_sh_mask.h26 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL
27 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
28 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L
29 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
30 #define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
31 #define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
32 #define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
33 #define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
34 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
35 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/OK3568_Linux_fs/kernel/tools/include/uapi/linux/
H A Dlirc.h13 #define PULSE_BIT 0x01000000
14 #define PULSE_MASK 0x00FFFFFF
16 #define LIRC_MODE2_SPACE 0x00000000
17 #define LIRC_MODE2_PULSE 0x01000000
18 #define LIRC_MODE2_FREQUENCY 0x02000000
19 #define LIRC_MODE2_TIMEOUT 0x03000000
21 #define LIRC_VALUE_MASK 0x00FFFFFF
22 #define LIRC_MODE2_MASK 0xFF000000
47 #define LIRC_MODE_RAW 0x00000001
48 #define LIRC_MODE_PULSE 0x00000002
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/
H A Dlirc.h13 #define PULSE_BIT 0x01000000
14 #define PULSE_MASK 0x00FFFFFF
16 #define LIRC_MODE2_SPACE 0x00000000
17 #define LIRC_MODE2_PULSE 0x01000000
18 #define LIRC_MODE2_FREQUENCY 0x02000000
19 #define LIRC_MODE2_TIMEOUT 0x03000000
21 #define LIRC_VALUE_MASK 0x00FFFFFF
22 #define LIRC_MODE2_MASK 0xFF000000
47 #define LIRC_MODE_RAW 0x00000001
48 #define LIRC_MODE_PULSE 0x00000002
[all …]

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