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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/sdram_inc/rk3308/
H A Dsdram-rk3308-lpddr2-detect-451.inc2 0,
3 0,
4 0,
5 0,
7 .ddr_type = 0x5,
8 .chn_cnt = 0x0,
9 .rank = 0x1,
10 .cs0_row = 0x0,
11 .cs1_row = 0x0,
12 .bank = 0x3,
[all …]
H A Dsdram-rk3308-lpddr2-detect-393.inc2 0,
3 0,
4 0,
5 0,
7 .ddr_type = 0x5,
8 .chn_cnt = 0x0,
9 .rank = 0x1,
10 .cs0_row = 0x0,
11 .cs1_row = 0x0,
12 .bank = 0x3,
[all …]
H A Dsdram-rk3308-ddr2-detect-393.inc2 0,
3 0,
4 0,
5 0,
7 .ddr_type = 0x2,
8 .chn_cnt = 0x0,
9 .rank = 0x1,
10 .cs0_row = 0x0,
11 .cs1_row = 0x0,
12 .bank = 0x3,
[all …]
H A Dsdram-rk3308-ddr3-detect-393.inc2 0,
3 0,
4 0,
5 0,
7 .ddr_type = 0x3,
8 .chn_cnt = 0x0,
9 .rank = 0x1,
10 .cs0_row = 0x0,
11 .cs1_row = 0x0,
12 .bank = 0x3,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/gdm724x/
H A Dhci_packet.h15 #define NIC_TYPE_NIC0 0x00000010
16 #define NIC_TYPE_NIC1 0x00000011
17 #define NIC_TYPE_NIC2 0x00000012
18 #define NIC_TYPE_NIC3 0x00000013
19 #define NIC_TYPE_ARP 0x00000100
20 #define NIC_TYPE_ICMPV6 0x00000200
21 #define NIC_TYPE_MASK 0x0000FFFF
22 #define NIC_TYPE_F_IPV4 0x00010000
23 #define NIC_TYPE_F_IPV6 0x00020000
24 #define NIC_TYPE_F_DHCP 0x00040000
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/function_types/detail/encoding/
H A Ddef.hpp13 // bit 0: callable builtin
22 #define BOOST_FT_type_mask 0x000000ff // 1111 1111
23 #define BOOST_FT_callable_builtin 0x00000001 // 0000 0001
24 #define BOOST_FT_non_member 0x00000002 // 0000 0010
25 #define BOOST_FT_function 0x00000007 // 0000 0111
26 #define BOOST_FT_pointer 0x0000000b // 0000 1011
27 #define BOOST_FT_reference 0x00000013 // 0001 0011
28 #define BOOST_FT_non_member_callable_builtin 0x00000003 // 0000 0011
29 #define BOOST_FT_member_pointer 0x00000020 // 0010 0000
30 #define BOOST_FT_member_function_pointer 0x00000061 // 0110 0001
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c36 #define MC_CG_ARB_FREQ_F0 0x0a
37 #define MC_CG_ARB_FREQ_F1 0x0b
38 #define MC_CG_ARB_FREQ_F2 0x0c
39 #define MC_CG_ARB_FREQ_F3 0x0d
41 #define MC_CG_SEQ_DRAMCONF_S0 0x05
42 #define MC_CG_SEQ_DRAMCONF_S1 0x06
43 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
44 #define MC_CG_SEQ_YCLK_RESUME 0x0a
46 #define SMC_RAM_END 0x8000
61 0x000008f8, 0x00000010, 0xffffffff,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Darmcoremodule.h15 #define CM_BASE 0x10000000
20 #define OS_CTRL 0x0000000C
21 #define CMMASK_REMAP 0x00000005 /* set remap & led */
22 #define CMMASK_RESET 0x00000008
23 #define OS_LOCK 0x00000014
24 #define CMVAL_LOCK1 0x0000A000 /* locking value */
25 #define CMVAL_LOCK2 0x0000005F /* locking value */
26 #define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
27 #define OS_SDRAM 0x00000020
28 #define OS_INIT 0x00000024
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/include/asm/
H A Dftrace.h50 #define JALR_SIGN_MASK (0x00000800)
51 #define JALR_OFFSET_MASK (0x00000fff)
52 #define AUIPC_OFFSET_MASK (0xfffff000)
53 #define AUIPC_PAD (0x00001000)
55 #define JALR_BASIC (0x000080e7)
56 #define AUIPC_BASIC (0x00000097)
57 #define NOP4 (0x00000013)
61 call[0] = to_auipc_insn((unsigned int)((unsigned long)callee - \
65 } while (0)
/OK3568_Linux_fs/kernel/drivers/soc/atmel/
H A Dsoc.h35 #define AT91RM9200_CIDR_MATCH 0x09290780
37 #define AT91SAM9260_CIDR_MATCH 0x019803a0
38 #define AT91SAM9261_CIDR_MATCH 0x019703a0
39 #define AT91SAM9263_CIDR_MATCH 0x019607a0
40 #define AT91SAM9G20_CIDR_MATCH 0x019905a0
41 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
42 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0
43 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0
44 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0
45 #define SAM9X60_CIDR_MATCH 0x019b35a0
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddmacgp102.c37 nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push); in gp102_disp_dmac_init()
38 nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000); in gp102_disp_dmac_init()
39 nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001); in gp102_disp_dmac_init()
40 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); in gp102_disp_dmac_init()
41 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); in gp102_disp_dmac_init()
42 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); in gp102_disp_dmac_init()
46 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000)) in gp102_disp_dmac_init()
48 ) < 0) { in gp102_disp_dmac_init()
50 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gp102_disp_dmac_init()
54 return 0; in gp102_disp_dmac_init()
H A Ddmacgv100.c31 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle()
33 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_dmac_idle()
34 if ((stat & 0x000f0000) == 0x00040000) in gv100_disp_dmac_idle()
35 return 0; in gv100_disp_dmac_idle()
46 chan->chid.user << 25 | 0x00000040); in gv100_disp_dmac_bind()
53 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_fini()
54 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_fini()
55 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); in gv100_disp_dmac_fini()
57 nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); in gv100_disp_dmac_fini()
58 chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); in gv100_disp_dmac_fini()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/function_types/detail/pp_tags/
H A Dpreprocessed.hpp13 typedef detail::property_tag<0x00000200,0x00000300> non_variadic;
14 typedef detail::property_tag<0x00000100,0x00000300> variadic;
15 typedef detail::property_tag<0,0x00000400> non_const;
16 typedef detail::property_tag<0x00000400,0x00000400> const_qualified;
17 typedef detail::property_tag<0,0x00000800> non_volatile;
18 typedef detail::property_tag<0x00000800,0x00000800> volatile_qualified;
19 typedef detail::property_tag<0x00008000,0x00ff8000> default_cc;
20 typedef detail::property_tag<0 , 3072> non_cv;
21 typedef detail::property_tag<0x00000400 , 3072> const_non_volatile;
22 typedef detail::property_tag<0x00000800, 3072> volatile_non_const;
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/ap325rxa/
H A Dlowlevel_init.S102 mov #0, r0
108 DRVCRA_D: .word 0x4555
109 DRVCRB_D: .word 0x0005
114 RWTCSR_D1: .word 0xa507
115 RWTCSR_D2: .word 0xa504
116 RWTCNT_D: .word 0x5a00
118 FRQCR_D: .long 0x0b04474a
126 SBSC_SDMR3_A1: .long 0xfe510000
127 SBSC_SDMR3_A2: .long 0xfe500242
128 SBSC_SDMR3_A3: .long 0xfe5c0042
[all …]

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