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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra20-acer-a500-picasso.dts36 memory@0 {
37 reg = <0x00000000 0x40000000>;
47 reg = <0x2ffe0000 0x10000>; /* 64kB */
48 console-size = <0x8000>; /* 32kB */
49 record-size = <0x400>; /* 1kB */
55 alloc-ranges = <0x30000000 0x10000000>;
56 size = <0x10000000>; /* 256MiB */
67 port@0 {
91 pinctrl-0 = <&state_default>;
406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra20-colibri.dtsi11 memory@0 {
17 reg = <0x00000000 0x10000000>;
32 pinctrl-0 = <&state_default>;
424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
440 nand@0 {
441 reg = <0>;
449 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
477 reg = <0x34>;
506 regulator-name = "VDD_CPU_1.0V";
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/atmel/
H A Dsoc.h35 #define AT91RM9200_CIDR_MATCH 0x09290780
37 #define AT91SAM9260_CIDR_MATCH 0x019803a0
38 #define AT91SAM9261_CIDR_MATCH 0x019703a0
39 #define AT91SAM9263_CIDR_MATCH 0x019607a0
40 #define AT91SAM9G20_CIDR_MATCH 0x019905a0
41 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
42 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0
43 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0
44 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0
45 #define SAM9X60_CIDR_MATCH 0x019b35a0
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcla0b5.h27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
[all …]
H A Dcl917d.h28 #define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0…
29 #define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0
30 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
31 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
32 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
33 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
34 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
36 #define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
37 #define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
38 #define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
[all …]
H A Dcl507d.h27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000
28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
37 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
38 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
[all …]
H A Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/OK3568_Linux_fs/kernel/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/phydm/rtl8188e/
H A Dhalhwimg8188e_bb.c31 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ in check_positive()
42 u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; in check_positive()
45 (dm->support_interface & 0xF0) << 16 | in check_positive()
48 (dm->support_interface & 0x0F) << 8 | in check_positive()
51 u32 driver2 = (dm->type_glna & 0xFF) << 0 | in check_positive()
52 (dm->type_gpa & 0xFF) << 8 | in check_positive()
53 (dm->type_alna & 0xFF) << 16 | in check_positive()
54 (dm->type_apa & 0xFF) << 24; in check_positive()
56 u32 driver3 = 0; in check_positive()
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | in check_positive()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/hal/phydm/rtl8188e/
H A Dhalhwimg8188e_bb.c35 u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ in CheckPositive()
43 (pDM_Odm->SupportInterface & 0xF0) << 16 | in CheckPositive()
46 (pDM_Odm->SupportInterface & 0x0F) << 8 | in CheckPositive()
49 u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | in CheckPositive()
50 (pDM_Odm->TypeGPA & 0xFF) << 8 | in CheckPositive()
51 (pDM_Odm->TypeALNA & 0xFF) << 16 | in CheckPositive()
52 (pDM_Odm->TypeAPA & 0xFF) << 24; in CheckPositive()
54 u4Byte driver3 = 0; in CheckPositive()
56 u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | in CheckPositive()
57 (pDM_Odm->TypeGPA & 0xFF00) | in CheckPositive()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/renesas/
H A Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/sound/
H A Dcompress_params.h64 #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001)
65 #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002)
66 #define SND_AUDIOCODEC_AMR ((__u32) 0x00000003)
67 #define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004)
68 #define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005)
69 #define SND_AUDIOCODEC_AAC ((__u32) 0x00000006)
70 #define SND_AUDIOCODEC_WMA ((__u32) 0x00000007)
71 #define SND_AUDIOCODEC_REAL ((__u32) 0x00000008)
72 #define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009)
73 #define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A)
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/sound/
H A Dcompress_params.h64 #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001)
65 #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002)
66 #define SND_AUDIOCODEC_AMR ((__u32) 0x00000003)
67 #define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004)
68 #define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005)
69 #define SND_AUDIOCODEC_AAC ((__u32) 0x00000006)
70 #define SND_AUDIOCODEC_WMA ((__u32) 0x00000007)
71 #define SND_AUDIOCODEC_REAL ((__u32) 0x00000008)
72 #define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009)
73 #define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/OK3568_Linux_fs/kernel/include/uapi/sound/
H A Dcompress_params.h64 #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001)
65 #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002)
66 #define SND_AUDIOCODEC_AMR ((__u32) 0x00000003)
67 #define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004)
68 #define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005)
69 #define SND_AUDIOCODEC_AAC ((__u32) 0x00000006)
70 #define SND_AUDIOCODEC_WMA ((__u32) 0x00000007)
71 #define SND_AUDIOCODEC_REAL ((__u32) 0x00000008)
72 #define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009)
73 #define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A)
[all …]

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