| /OK3568_Linux_fs/u-boot/include/bedbug/ |
| H A D | tables.h | 16 /*----- ------ ----- ----- ---- ------------ */
18 { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
19 { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
20 { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
21 { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
22 { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
23 { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
24 { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
25 { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
26 { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
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| /OK3568_Linux_fs/kernel/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
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| /OK3568_Linux_fs/kernel/arch/powerpc/lib/ |
| H A D | feature-fixups-test.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
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| /OK3568_Linux_fs/kernel/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-meta-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvhw/class/ |
| H A D | cl502d.h | 2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
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| H A D | cl902d.h | 2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
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| H A D | cl5039.h | 2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
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| /OK3568_Linux_fs/kernel/arch/arm/include/asm/hardware/ |
| H A D | entry-macro-iomd.S | 2 * arch/arm/include/asm/hardware/entry-macro-iomd.S
4 * Low-level IRQ helper macros for IOC/IOMD based platforms
17 teq \irqstat, #0
21 teqeq \irqstat, #0
26 teqeq \irqstat, #0
30 teqeq \irqstat, #0
35 teqeq \irqstat, #0
45 irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
62 irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
79 irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
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| /OK3568_Linux_fs/kernel/drivers/net/dsa/sja1105/ |
| H A D | sja1105_ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #define SJA1105_SIZE_MAC_AREA (0x02 * 4)
7 #define SJA1105_SIZE_HL1_AREA (0x10 * 4)
8 #define SJA1105_SIZE_HL2_AREA (0x4 * 4)
9 #define SJA1105_SIZE_QLEVEL_AREA (0x8 * 4) /* 0x4 to 0xB */
10 #define SJA1105_SIZE_ETHER_AREA (0x17 * 4)
107 sja1105_unpack(p + 0x0, &status->n_runt, 31, 24, 4); in sja1105_port_status_mac_unpack()
108 sja1105_unpack(p + 0x0, &status->n_soferr, 23, 16, 4); in sja1105_port_status_mac_unpack()
109 sja1105_unpack(p + 0x0, &status->n_alignerr, 15, 8, 4); in sja1105_port_status_mac_unpack()
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| /OK3568_Linux_fs/kernel/drivers/infiniband/hw/hns/ |
| H A D | hns_roce_hw_v2.h | 2 * Copyright (c) 2016-2017 Hisilicon Limited.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
48 #define HNS_ROCE_V2_MAX_QP_NUM 0x100000
49 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
50 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
51 #define HNS_ROCE_V2_MAX_SRQ 0x100000
52 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
54 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
55 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/nvidia/ |
| H A D | nv_dma.h | 8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
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| /OK3568_Linux_fs/kernel/drivers/infiniband/hw/i40iw/ |
| H A D | i40iw_register.h | 3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
41 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
42 #define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
44 #define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
45 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
46 #define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
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| /OK3568_Linux_fs/output/sessions/2025-06-05_23-17-21/ |
| H A D | initial.env | |
| H A D | final.env | |
| /OK3568_Linux_fs/output/sessions/2025-06-06_01-57-56/ |
| H A D | initial.env | |
| H A D | final.env | |
| /OK3568_Linux_fs/output/ |
| H A D | initial.env | |
| H A D | final.env | |
| /OK3568_Linux_fs/kernel/arch/mips/include/asm/octeon/ |
| H A D | cvmx-ciu2-defs.h | 7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 …ine CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * …
32 …ine CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * …
33 … CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * …
34 …CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * …
35 …CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * …
36 …_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * …
37 …_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * …
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| /OK3568_Linux_fs/kernel/arch/alpha/include/asm/ |
| H A D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
32 .prologue 0 \n\
36 ldq $0,0($17) \n\
37 ldq $1,0($18) \n\
54 xor $0,$1,$0 # 7 cycles from $1 load \n\
58 stq $0,0($17) \n\
87 .prologue 0 \n\
91 ldq $0,0($17) \n\
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| /OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/binutils/binutils/ |
| H A D | 0008-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | 3 Date: Sat, 11 Jun 2016 22:08:29 -0500
6 The wait mnemonic for ppc targets is incorrectly assembled into 0x7c00003c due
10 Upstream-Status: Pending
11 Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com>
12 ---
13 opcodes/ppc-opc.c | 4 +---
14 1 file changed, 1 insertion(+), 3 deletions(-)
16 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
18 --- a/opcodes/ppc-opc.c
19 +++ b/opcodes/ppc-opc.c
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| /OK3568_Linux_fs/u-boot/board/keymile/km_arm/ |
| H A D | kwbimage_256M8_1.cfg | 7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
21 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
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| H A D | kwbimage_128M16_1.cfg | 10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
19 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7603/ |
| H A D | regs.h | 1 /* SPDX-License-Identifier: ISC */
6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
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| /OK3568_Linux_fs/kernel/arch/m68k/include/asm/ |
| H A D | bitops.h | 22 * ColdFire - supports standard bset/bclr/bchg with register operand only
23 * 68000 - supports standard bset/bclr/bchg with memory operand
24 * >= 68020 - also supports the bfset/bfclr/bfchg instructions
33 char *p = (char *)vaddr + (nr ^ 31) / 8; in bset_reg_set_bit()
35 __asm__ __volatile__ ("bset %1,(%0)" in bset_reg_set_bit()
43 char *p = (char *)vaddr + (nr ^ 31) / 8; in bset_mem_set_bit()
45 __asm__ __volatile__ ("bset %1,%0" in bset_mem_set_bit()
52 __asm__ __volatile__ ("bfset %1{%0:#1}" in bfset_mem_set_bit()
54 : "d" (nr ^ 31), "o" (*vaddr) in bfset_mem_set_bit()
73 char *p = (char *)vaddr + (nr ^ 31) / 8; in bclr_reg_clear_bit()
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