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/OK3568_Linux_fs/kernel/sound/drivers/
H A Dserial-u16550.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Added support for the Midiator MS-124T and for the MS-124W in
17 * More documentation can be found in serial-u16550.txt.
40 #define SNDRV_SERIAL_MS124T 1 /* Midiator MS-124T */
41 #define SNDRV_SERIAL_MS124W_SA 2 /* Midiator MS-124W in S/A mode */
42 #define SNDRV_SERIAL_MS124W_MB 3 /* Midiator MS-124W in M/B mode */
47 "MS-124T",
48 "MS-124W S/A",
49 "MS-124W M/B",
54 #define SNDRV_SERIAL_DROPBUFF 1 /* Non-blocking discard operation */
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/OK3568_Linux_fs/u-boot/drivers/serial/
H A DKconfig11 Select a default baudrate, where "default" has a driver-specific
12 meaning of either setting the baudrate for the early debug UART
19 # non-dm serial code
32 In very space-constrained devices even the full UART driver is too
33 large. In this case the debug UART can still be used in some cases.
34 This option enables the full UART in U-Boot, so if is it disabled,
35 the full UART driver will be omitted, thus saving space.
42 In very space-constrained devices even the full UART driver is too
43 large. In this case the debug UART can still be used in some cases.
44 This option enables the full UART in SPL, so if is it disabled,
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H A Dmcfuart.c2 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
8 * SPDX-License-Identifier: GPL-2.0+
12 * Minimal serial functions needed to use one of the uart ports
22 #include <asm/uart.h>
28 static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate) in mcf_serial_init_common() argument
34 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ in mcf_serial_init_common()
35 writeb(UART_UCR_RESET_RX, &uart->ucr); in mcf_serial_init_common()
36 writeb(UART_UCR_RESET_TX, &uart->ucr); in mcf_serial_init_common()
37 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in mcf_serial_init_common()
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H A Dserial_s5p.c8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/uart.h>
34 u8 port_id; /* uart port number */
42 * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
63 static void __maybe_unused s5p_serial_init(struct s5p_uart *uart) in s5p_serial_init() argument
66 writel(0x3, &uart->ufcon); in s5p_serial_init()
67 writel(0, &uart->umcon); in s5p_serial_init()
69 writel(0x3, &uart->ulcon); in s5p_serial_init()
71 writel(0x245, &uart->ucon); in s5p_serial_init()
74 static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, in s5p_serial_baud() argument
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H A Dserial_pxa.c8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
20 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/arch/pxa-regs.h>
25 #include <asm/arch/regs-uart.h>
70 writel(0, &uart_regs->ier); in pxa_setbrg_common()
71 writel(0, &uart_regs->fcr); in pxa_setbrg_common()
74 writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr); in pxa_setbrg_common()
75 writel(divider & 0xff, &uart_regs->dll); in pxa_setbrg_common()
76 writel(divider >> 8, &uart_regs->dlh); in pxa_setbrg_common()
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/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Dmen_z135_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
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H A Dtimbuart.c1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
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H A Darc_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <fabio.estevam@nxp.com>
13 - $ref: "serial.yaml"
14 - $ref: "rs485.yaml"
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
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H A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
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H A Dmtk-uart.txt1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible should contain:
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
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H A Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
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H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
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H A Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P and Exynos SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - samsung,s3c2410-uart
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H A Dsirf-uart.txt4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
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/OK3568_Linux_fs/kernel/drivers/tty/serial/8250/
H A D8250_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
48 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
49 * is unsafe when used on edge-triggered interrupts.
63 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * line has been de-asserted.
117 spin_lock(&i->lock); in serial8250_interrupt()
119 l = i->head; in serial8250_interrupt()
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H A D8250_tegra.c1 // SPDX-License-Identifier: GPL-2.0+
30 status = p->serial_in(p, UART_LSR); in tegra_uart_handle_break()
32 status = p->serial_in(p, UART_RX); in tegra_uart_handle_break()
35 if (--tmout == 0) in tegra_uart_handle_break()
44 struct tegra_uart *uart; in tegra_uart_probe() local
49 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
50 if (!uart) in tegra_uart_probe()
51 return -ENOMEM; in tegra_uart_probe()
56 spin_lock_init(&port->lock); in tegra_uart_probe()
58 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | in tegra_uart_probe()
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H A D8250_ingenic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
47 return readl(port->membase + (offset << 2)); in early_in()
52 writel(value, port->membase + (offset << 2)); in early_out()
69 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
87 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
93 struct uart_port *port = &dev->port; in ingenic_early_console_setup()
97 if (!dev->port.membase) in ingenic_early_console_setup()
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H A D8250_lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for NXP LPC18xx/43xx UART
43 if (rs485->flags & SER_RS485_ENABLED) in lpc18xx_rs485_config()
44 memset(rs485->padding, 0, sizeof(rs485->padding)); in lpc18xx_rs485_config()
48 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | in lpc18xx_rs485_config()
51 if (rs485->flags & SER_RS485_ENABLED) { in lpc18xx_rs485_config()
55 if (rs485->flags & SER_RS485_RTS_ON_SEND) { in lpc18xx_rs485_config()
57 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpc18xx_rs485_config()
59 rs485->flags |= SER_RS485_RTS_AFTER_SEND; in lpc18xx_rs485_config()
63 if (rs485->delay_rts_after_send) { in lpc18xx_rs485_config()
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H A D8250_pxa.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
38 serial8250_suspend_port(data->line); in serial_pxa_suspend()
47 serial8250_resume_port(data->line); in serial_pxa_resume()
57 { .compatible = "mrvl,pxa-uart", },
58 { .compatible = "mrvl,mmp-uart", },
63 /* Uart divisor latch write */
83 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
86 clk_prepare_enable(data->clk); in serial_pxa_pm()
88 clk_disable_unprepare(data->clk); in serial_pxa_pm()
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/OK3568_Linux_fs/kernel/arch/mips/kernel/
H A Dcps-vec-ns16550.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
46 * @a0: pointer to NULL-terminated ASCII string
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
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/OK3568_Linux_fs/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c2 * (C) Copyright 2000-2003
4 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
6 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/uart.h>
43 &sdp->cs0); in dram_init()
45 &sdp->cs1); in dram_init()
51 __raw_writel(0x33211530, &sdp->cfg1); in dram_init()
52 __raw_writel(0x56570000, &sdp->cfg2); in dram_init()
54 __raw_writel(0xE1462C02, &sdp->ctrl); in dram_init()
57 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
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/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
96 1 - undefined instruction events
97 2 - system calls
98 4 - invalid data aborts
99 8 - SIGSEGV faults
100 16 - SIGBUS faults
104 bool "Kernel low-level debugging functions (read help!)"
112 UART definition, as specified below. Attempting to boot the kernel
117 prompt "Kernel low-level debugging port"
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/OK3568_Linux_fs/kernel/arch/arm/include/debug/
H A Dtegra.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
12 * Portions based on mach-omap2's debug-macro.S
13 * Copyright (C) 1994-1999 Russell King
40 * Must be section-aligned since a section mapping is used early on.
41 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
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/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
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