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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1126-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
11 a7m0_pins: a7m0-pins {
12 rockchip,pins =
18 a7m1_pins: a7m1-pins {
19 rockchip,pins =
27 acodec_pins: acodec-pins {
28 rockchip,pins =
46 auddsm_pins: auddsm-pins {
[all …]
H A Drk3588s-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 auddsm_pins: auddsm-pins {
16 rockchip,pins =
29 bt1120_pins: bt1120-pins {
30 rockchip,pins =
69 can0m0_pins: can0m0-pins {
70 rockchip,pins =
77 can0m1_pins: can0m1-pins {
[all …]
H A Drk3562-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 camm0_pins: camm0-pins {
16 rockchip,pins =
23 camm1_pins: camm1-pins {
24 rockchip,pins =
31 cam_clk2_out: cam-clk2-out {
32 rockchip,pins =
36 cam_clk3_out: cam-clk3-out {
[all …]
H A Drk3568-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 acodec_pins: acodec-pins {
16 rockchip,pins =
34 audiopwmout_pins: audiopwmout-pins {
35 rockchip,pins =
43 audiopwmoutdiff_pins: audiopwmoutdiff-pins {
44 rockchip,pins =
56 bt656m0_pins: bt656m0-pins {
[all …]
H A Drk3528-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 arm_pins: arm-pins {
16 rockchip,pins =
23 can0m0_pins: can0m0-pins {
24 rockchip,pins =
31 can0m1_pins: can0m1-pins {
32 rockchip,pins =
41 can1m0_pins: can1m0-pins {
[all …]
H A Drv1106-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 adc_pins: adc-pins {
16 rockchip,pins =
25 avs_pins: avs-pins {
26 rockchip,pins =
33 clk_32k: clk-32k {
34 rockchip,pins =
38 clk_refout: clk-refout {
[all …]
H A Dtegra124-nyan-big.dts1 /dts-v1/;
3 #include "tegra124-nyan.dtsi"
6 model = "Acer Chromebook 13 CB5-311";
7 compatible = "google,nyan-big", "nvidia,tegra124";
29 stdout-path = &uarta;
34 display-timings {
36 clock-frequency = <69500000>;
39 hsync-len = <32>;
40 hfront-porch = <48>;
41 hback-porch = <20>;
[all …]
H A Drk3588-vccio3-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
14 clk32k_out1: clk32k-out1 {
15 rockchip,pins =
23 eth0_pins: eth0-pins {
24 rockchip,pins =
32 fspim1_pins: fspim1-pins {
33 rockchip,pins =
48 fspim1_cs1: fspim1-cs1 {
49 rockchip,pins =
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dmsm8996-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
11 pins = "gpio54";
16 pins = "gpio54";
17 drive-strength = <2>; /* 2 mA */
18 bias-pull-down; /* pull down */
19 input-enable;
27 pins = "gpio64";
31 pins = "gpio64";
32 drive-strength = <16>;
[all …]
H A Dmsm8916-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default {
10 pins = "gpio0", "gpio1", "gpio2", "gpio3";
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep {
18 pins = "gpio0", "gpio1", "gpio2", "gpio3";
21 drive-strength = <2>;
22 bias-pull-down;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588s-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rk3588s-pinconf.dtsi"
15 /omit-if-no-ref/
16 auddsm_pins: auddsm-pins {
17 rockchip,pins =
30 /omit-if-no-ref/
31 bt1120_pins: bt1120-pins {
32 rockchip,pins =
71 /omit-if-no-ref/
[all …]
H A Drk3562-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 camm0_clk0_out: camm0-clk0-out {
17 rockchip,pins =
22 /omit-if-no-ref/
23 camm0_clk1_out: camm0-clk1-out {
24 rockchip,pins =
29 /omit-if-no-ref/
[all …]
H A Drk3528-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 arm_pins: arm-pins {
17 rockchip,pins =
24 /omit-if-no-ref/
25 clkm0_32k_out: clkm0-32k-out {
26 rockchip,pins =
31 /omit-if-no-ref/
[all …]
H A Drk3568-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 acodec_pins: acodec-pins {
17 rockchip,pins =
36 /omit-if-no-ref/
37 audiopwm_lout: audiopwm-lout {
38 rockchip,pins =
43 /omit-if-no-ref/
[all …]
H A Drk3308bs-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 pcfg_pull_none_0_4ma: pcfg-pull-none-0-4ma {
9 bias-disable;
10 drive-strength-s = <4>;
12 pcfg_pull_none_0_4ma_smt: pcfg-pull-none-0-4ma-smt {
13 bias-disable;
14 drive-strength-s = <4>;
15 input-schmitt-enable;
17 pcfg_pull_up_0_4ma: pcfg-pull-up-0-4ma {
18 bias-pull-up;
[all …]
H A Drk3588-vccio3-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 clk32k_out1: clk32k-out1 {
17 rockchip,pins =
25 /omit-if-no-ref/
26 eth0_pins: eth0-pins {
27 rockchip,pins =
35 /omit-if-no-ref/
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1126-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 acodec_pins: acodec-pins {
17 rockchip,pins =
35 /omit-if-no-ref/
36 auddsm_pins: auddsm-pins {
37 rockchip,pins =
49 /omit-if-no-ref/
[all …]
H A Drk3288-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
11 hdmi_gpio: hdmi-gpio {
12 rockchip,pins =
17 hdmi_cec_c0: hdmi-cec-c0 {
18 rockchip,pins =
22 hdmi_cec_c7: hdmi-cec-c7 {
23 rockchip,pins =
27 hdmi_ddc: hdmi-ddc {
[all …]
H A Drv1106-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 adc_pins: adc-pins {
17 rockchip,pins =
26 /omit-if-no-ref/
27 avs_pins: avs-pins {
28 rockchip,pins =
35 /omit-if-no-ref/
[all …]
H A Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdc4_gpios: sdc4-gpios {
6 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
11 sdcc1_pins: sdcc1-pin-active {
13 pins = "sdc1_clk";
14 drive-strengh = <16>;
15 bias-disable;
19 pins = "sdc1_cmd";
20 drive-strengh = <10>;
21 bias-pull-up;
[all …]
H A Dtegra124-nyan-blaze.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-blaze-emc.dtsi"
10 compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
11 "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
12 "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
13 "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
14 "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
15 "google,nyan-blaze-rev0", "google,nyan-blaze",
[all …]
H A Dtegra124-nyan-big.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-big-emc.dtsi"
9 model = "Acer Chromebook 13 CB5-311";
10 compatible = "google,nyan-big-rev7", "google,nyan-big-rev6",
11 "google,nyan-big-rev5", "google,nyan-big-rev4",
12 "google,nyan-big-rev3", "google,nyan-big-rev2",
13 "google,nyan-big-rev1", "google,nyan-big-rev0",
14 "google,nyan-big", "google,nyan", "nvidia,tegra124";
[all …]
H A Dtegra30-beaver.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
19 stdout-path = "serial0:115200n8";
29 avdd-pexa-supply = <&ldo1_reg>;
30 vdd-pexa-supply = <&ldo1_reg>;
31 avdd-pexb-supply = <&ldo1_reg>;
32 vdd-pexb-supply = <&ldo1_reg>;
33 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
H A Dlpc4357-myd-lpc4357.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2571.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra210-p2530.dtsi"
12 pinctrl-names = "boot";
13 pinctrl-0 = <&state_boot>;
17 nvidia,pins = "pex_l0_rst_n_pa0";
20 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
21 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
22 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
[all …]

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