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/rk3399_rockchip-uboot/board/freescale/mpc832xemds/
H A DREADME2 -----------------------------------------
4 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
11 and some of those signals may be high-bit-number-0 too. Heed
17 SW3 is switch 18 as silk-screened onto the board.
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
30 SW5[1-8]= 0010_0110 (Boot from high end)
31 SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
32 SW7[1-8]= 1000_0011 (QE PLL setting)
35 J1 1-2 (ETH3_TXER)
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/rk3399_rockchip-uboot/board/mpr2/
H A Dmpr2.c7 * SPDX-License-Identifier: GPL-2.0+
26 /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */ in board_init()
30 /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */ in board_init()
34 /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */ in board_init()
38 /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */ in board_init()
42 /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */ in board_init()
61 * GPI+: (10) General Purpose Input with internal pull-up in board_init()
62 *------------------------------------------------------- in board_init()
95 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; in board_init()
/rk3399_rockchip-uboot/
H A D.travis.yml2 # SPDX-License-Identifier: GPL-2.0+
4 # build U-Boot on Travis CI - https://travis-ci.org/
14 - cppcheck
15 - sloccount
16 - sparse
17 - bc
18 - build-essential
19 - libsdl1.2-dev
20 - python
21 - python-virtualenv
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/rk3399_rockchip-uboot/board/gateworks/gw_ventana/
H A Dgw_ventana.c6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/mx6-pins.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/sata.h>
19 #include <asm/mach-imx/spi.h>
20 #include <asm/mach-imx/video.h>
107 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
116 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
199 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; in board_spi_cs_gpio()
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