1 /*
2 * Copyright (c) 2021-2026, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef __DDR_INTERNAL_H__
8 #define __DDR_INTERNAL_H__
9
10 #include <lib/mmio.h>
11 #include <ddr_mc_if.h>
12 #include <ddr_phy_regs.h>
13
14 #define MC_PHYSET_NUM (4)
15 #define SWIZZLE_MC_NUM (9)
16 #define SIZZLE_PHY_NUM (16)
17
read_mc_reg(uint32_t offset)18 static inline uint32_t read_mc_reg(uint32_t offset)
19 {
20 return mmio_read_32(DDR_MC_BASE + offset);
21 }
22
write_mc_reg(uint32_t offset,uint32_t val)23 static inline void write_mc_reg(uint32_t offset, uint32_t val)
24 {
25 mmio_write_32(DDR_MC_BASE + offset, val);
26 }
27
rmw_mc_reg(uint32_t offset,uint32_t mask,uint32_t val)28 static inline void rmw_mc_reg(uint32_t offset, uint32_t mask, uint32_t val)
29 {
30 write_mc_reg(offset, (read_mc_reg(offset) & mask) | val);
31 }
32
read_phy_reg(uint32_t offset)33 static inline uint32_t read_phy_reg(uint32_t offset)
34 {
35 return mmio_read_32(DDR_PHY_BASE + offset);
36 }
37
write_phy_reg(uint32_t offset,uint32_t val)38 static inline void write_phy_reg(uint32_t offset, uint32_t val)
39 {
40 mmio_write_32(DDR_PHY_BASE + offset, val);
41 }
42
rmw_phy_reg(uint32_t offset,uint32_t mask,uint32_t val)43 static inline void rmw_phy_reg(uint32_t offset, uint32_t mask, uint32_t val)
44 {
45 write_phy_reg(offset, (read_phy_reg(offset) & mask) | val);
46 }
47
ddr_ctrl_reten_en_n(bool en)48 static inline void ddr_ctrl_reten_en_n(bool en)
49 {
50 write_phy_reg(DDRPHY_R79, en ? BIT(1) : 0);
51 }
52
53 extern const uint32_t mc_init_tbl[MC_INIT_NUM][2];
54 extern const uint32_t mc_odt_pins_tbl[4];
55 extern const uint32_t mc_mr1_tbl[2];
56 extern const uint32_t mc_mr2_tbl[2];
57 extern const uint32_t mc_mr5_tbl[2];
58 extern const uint32_t mc_mr6_tbl[2];
59 extern const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2];
60 extern const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2];
61 extern const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2];
62 extern const char ddr_an_version[];
63
64 #endif /* __DDR_INTERNAL_H__ */
65