1 /*
2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef ARCH_FEATURES_H
8 #define ARCH_FEATURES_H
9
10 #include <stdbool.h>
11
12 #include <arch_helpers.h>
13 #include <common/feat_detect.h>
14 #include <lib/cpus/errata.h>
15 #include <lib/el3_runtime/context_mgmt.h>
16 #include <lib/el3_runtime/cpu_data.h>
17
18 #if ENABLE_RME
19 #define FEAT_ENABLE_ALL_WORLDS \
20 ((1u << CPU_CONTEXT_SECURE) | \
21 (1u << CPU_CONTEXT_NS) | \
22 (1u << CPU_CONTEXT_REALM))
23 #define FEAT_ENABLE_REALM (1 << CPU_CONTEXT_REALM)
24 #else
25 #define FEAT_ENABLE_ALL_WORLDS \
26 ((1u << CPU_CONTEXT_SECURE) | \
27 (1u << CPU_CONTEXT_NS))
28 #define FEAT_ENABLE_REALM U(0)
29 #endif
30
31 #define FEAT_ENABLE_SECURE (1 << CPU_CONTEXT_SECURE)
32 #define FEAT_ENABLE_NS (1 << CPU_CONTEXT_NS)
33
34 #define ISOLATE_FIELD(reg, feat, mask) \
35 ((unsigned int)(((reg) >> (feat)) & mask))
36
37 #define SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, world) \
38 (((guard) == 0U) || ((((enabled_worlds) >> (world)) & 1U) == 0U))
39
40
41 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
42 __attribute__((always_inline)) \
43 static inline bool is_ ## name ## _supported(void) \
44 { \
45 if ((guard) == FEAT_STATE_DISABLED) { \
46 return false; \
47 } \
48 if ((guard) == FEAT_STATE_ALWAYS) { \
49 return true; \
50 } \
51 return read_func(); \
52 }
53
54 /*
55 * CREATE_IDREG_UPDATE and CREATE_PERCPU_IDREG_UPDATE are two macros that
56 * generate the update_feat_abc_idreg_field() function based on how its
57 * corresponding ID register is cached.
58 * The function disables ID register fields related to a feature if the build
59 * flag for that feature is 0 or if the feature should be disabled for that
60 * world. If the particular field has to be disabled, its field in the cached
61 * ID register is set to 0.
62 *
63 * Note: For most ID register fields, a value of 0 represents
64 * the Unimplemented state, and hence we use this macro to show features
65 * disabled in EL3 as unimplemented to lower ELs. However, certain feature's
66 * ID Register fields (like ID_AA64MMFR4_EL1.E2H0) deviate from this convention,
67 * where 0 does not represent Unimplemented.
68 * For those features, a custom update_feat_abc_idreg_field()
69 * needs to be created. This custom function should set the field to the
70 * feature's unimplemented state value if the feature is disabled in EL3.
71 *
72 * For example:
73 *
74 * __attribute__((always_inline))
75 * static inline void update_feat_abc_idreg_field(size_t security_state)
76 * {
77 * if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) {
78 * per_world_context_t *per_world_ctx =
79 * &per_world_context[security_state];
80 * perworld_idregs_t *perworld_idregs = &(per_world_ctx->idregs);
81 *
82 * perworld_idregs->idreg &=
83 * ~((u_register_t)mask << idfield);
84 * perworld_idregs->idreg |=
85 * (((u_register_t)<unimplemented state value> & mask) << idfield);
86 * }
87 * }
88 */
89
90 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31)
91 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) \
92 __attribute__((always_inline)) \
93 static inline void update_ ## name ## _idreg_field(size_t security_state) \
94 { \
95 if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { \
96 per_world_context_t *per_world_ctx = \
97 &per_world_context[security_state]; \
98 perworld_idregs_t *perworld_idregs = &(per_world_ctx->idregs); \
99 perworld_idregs->idreg &= ~((u_register_t)mask << idfield); \
100 } \
101 }
102 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \
103 enabled_worlds) \
104 __attribute__((always_inline)) \
105 static inline void update_ ## name ## _idreg_field(size_t security_state) \
106 { \
107 if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { \
108 percpu_idregs_t *percpu_idregs = \
109 &(get_cpu_data(idregs[security_state]));\
110 percpu_idregs->idreg &= ~((u_register_t)mask << idfield); \
111 } \
112 }
113 #else
114 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds)
115 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \
116 enabled_worlds)
117 #endif
118
119 #define _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
120 __attribute__((always_inline)) \
121 static inline bool is_ ## name ## _present(void) \
122 { \
123 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
124 ? true : false; \
125 }
126
127 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \
128 enabled_worlds) \
129 _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
130 CREATE_IDREG_UPDATE(name, idreg, idfield, mask, 1U, enabled_worlds)
131
132 #define CREATE_PERCPU_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \
133 enabled_worlds) \
134 _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
135 CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, 1U, \
136 enabled_worlds)
137
138 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard, \
139 enabled_worlds) \
140 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \
141 enabled_worlds) \
142 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
143
144 #define CREATE_PERCPU_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard, \
145 enabled_worlds) \
146 CREATE_PERCPU_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \
147 enabled_worlds) \
148 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
149
150 /* +----------------------------+
151 * | Features supported |
152 * +----------------------------+
153 * | GENTIMER |
154 * +----------------------------+
155 * | FEAT_PAN |
156 * +----------------------------+
157 * | FEAT_VHE |
158 * +----------------------------+
159 * | FEAT_TTCNP |
160 * +----------------------------+
161 * | FEAT_UAO |
162 * +----------------------------+
163 * | FEAT_PACQARMA3 |
164 * +----------------------------+
165 * | FEAT_PAUTH |
166 * +----------------------------+
167 * | FEAT_TTST |
168 * +----------------------------+
169 * | FEAT_BTI |
170 * +----------------------------+
171 * | FEAT_MTE2 |
172 * +----------------------------+
173 * | FEAT_SSBS |
174 * +----------------------------+
175 * | FEAT_NMI |
176 * +----------------------------+
177 * | FEAT_GCS |
178 * +----------------------------+
179 * | FEAT_EBEP |
180 * +----------------------------+
181 * | FEAT_SEBEP |
182 * +----------------------------+
183 * | FEAT_SEL2 |
184 * +----------------------------+
185 * | FEAT_TWED |
186 * +----------------------------+
187 * | FEAT_FGT |
188 * +----------------------------+
189 * | FEAT_EC/ECV2 |
190 * +----------------------------+
191 * | FEAT_RNG |
192 * +----------------------------+
193 * | FEAT_TCR2 |
194 * +----------------------------+
195 * | FEAT_S2POE |
196 * +----------------------------+
197 * | FEAT_S1POE |
198 * +----------------------------+
199 * | FEAT_S2PIE |
200 * +----------------------------+
201 * | FEAT_S1PIE |
202 * +----------------------------+
203 * | FEAT_AMU/AMUV1P1 |
204 * +----------------------------+
205 * | FEAT_MPAM |
206 * +----------------------------+
207 * | FEAT_HCX |
208 * +----------------------------+
209 * | FEAT_RNG_TRAP |
210 * +----------------------------+
211 * | FEAT_RME |
212 * +----------------------------+
213 * | FEAT_SB |
214 * +----------------------------+
215 * | FEAT_CSV2_2/CSV2_3 |
216 * +----------------------------+
217 * | FEAT_SPE |
218 * +----------------------------+
219 * | FEAT_SVE |
220 * +----------------------------+
221 * | FEAT_RAS |
222 * +----------------------------+
223 * | FEAT_DIT |
224 * +----------------------------+
225 * | FEAT_SYS_REG_TRACE |
226 * +----------------------------+
227 * | FEAT_TRF |
228 * +----------------------------+
229 * | FEAT_NV2 |
230 * +----------------------------+
231 * | FEAT_BRBE |
232 * +----------------------------+
233 * | FEAT_TRBE |
234 * +----------------------------+
235 * | FEAT_SME/SME2 |
236 * +----------------------------+
237 * | FEAT_PMUV3 |
238 * +----------------------------+
239 * | FEAT_MTPMU |
240 * +----------------------------+
241 * | FEAT_FGT2 |
242 * +----------------------------+
243 * | FEAT_THE |
244 * +----------------------------+
245 * | FEAT_SCTLR2 |
246 * +----------------------------+
247 * | FEAT_D128 |
248 * +----------------------------+
249 * | FEAT_LS64_ACCDATA |
250 * +----------------------------+
251 * | FEAT_FPMR |
252 * +----------------------------+
253 * | FEAT_MOPS |
254 * +----------------------------+
255 * | FEAT_PAUTH_LR |
256 * +----------------------------+
257 * | FEAT_FGWTE3 |
258 * +----------------------------+
259 * | FEAT_MPAM_PE_BW_CTRL |
260 * +----------------------------+
261 * | FEAT_CPA2 |
262 * +----------------------------+
263 * | FEAT_AIE |
264 * +----------------------------+
265 * | FEAT_PFAR |
266 * +----------------------------+
267 * | FEAT_RME_GPC2 |
268 * +----------------------------+
269 * | FEAT_RME_GDI |
270 * +----------------------------+
271 * | FEAT_IDTE3 |
272 * +----------------------------+
273 * | FEAT_UINJ |
274 * +----------------------------+
275 * | FEAT_LSE |
276 * +----------------------------+
277 */
278
279 __attribute__((always_inline))
is_armv7_gentimer_present(void)280 static inline bool is_armv7_gentimer_present(void)
281 {
282 /* The Generic Timer is always present in an ARMv8-A implementation */
283 return true;
284 }
285
286 /* FEAT_PAN: Privileged access never */
287 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
288 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN,
289 FEAT_ENABLE_ALL_WORLDS)
290
291 /* FEAT_VHE: Virtualization Host Extensions */
292 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
293 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE,
294 FEAT_ENABLE_ALL_WORLDS)
295
296 /* FEAT_TTCNP: Translation table common not private */
297 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT,
298 ID_AA64MMFR2_EL1_CNP_MASK, 1U,
299 FEAT_ENABLE_ALL_WORLDS)
300
301 /* FEAT_UAO: User access override */
302 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT,
303 ID_AA64MMFR2_EL1_UAO_MASK, 1U,
304 FEAT_ENABLE_ALL_WORLDS)
305
306 /* If any of the fields is not zero, QARMA3 algorithm is present */
307 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0,
308 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
309 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U,
310 FEAT_ENABLE_ALL_WORLDS)
311
312 /* FEAT_PAUTH: Pointer Authentication */
313 __attribute__((always_inline))
is_feat_pauth_present(void)314 static inline bool is_feat_pauth_present(void)
315 {
316 uint64_t mask_id_aa64isar1 =
317 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
318 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
319 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
320 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
321
322 /*
323 * If any of the fields is not zero or QARMA3 is present,
324 * PAuth is present
325 */
326 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
327 is_feat_pacqarma3_present());
328 }
CREATE_FEATURE_SUPPORTED(feat_pauth,is_feat_pauth_present,ENABLE_PAUTH)329 CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH)
330 CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS)
331
332 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31)
333 __attribute__((always_inline))
334 static inline void update_feat_pauth_idreg_field(size_t security_state)
335 {
336 uint64_t mask_id_aa64isar1 =
337 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
338 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
339 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
340 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
341
342 uint64_t mask_id_aa64isar2 =
343 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_MASK) |
344 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_MASK);
345
346 per_world_context_t *per_world_ctx = &per_world_context[security_state];
347 perworld_idregs_t *perworld_idregs =
348 &(per_world_ctx->idregs);
349
350 if ((SHOULD_ID_FIELD_DISABLE(ENABLE_PAUTH, FEAT_ENABLE_NS,
351 security_state)) &&
352 (SHOULD_ID_FIELD_DISABLE(CTX_INCLUDE_PAUTH_REGS,
353 FEAT_ENABLE_ALL_WORLDS,
354 security_state))) {
355 perworld_idregs->id_aa64isar1_el1 &= ~(mask_id_aa64isar1);
356 perworld_idregs->id_aa64isar2_el1 &= ~(mask_id_aa64isar2);
357 }
358 }
359 #endif
360
361 /*
362 * FEAT_PAUTH_LR
363 * This feature has a non-standard discovery method so define this function
364 * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This
365 * feature is enabled with ENABLE_PAUTH when present.
366 */
367 __attribute__((always_inline))
is_feat_pauth_lr_present(void)368 static inline bool is_feat_pauth_lr_present(void)
369 {
370 /*
371 * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more
372 * of these is 0b0110 then the feature is present.
373 * 1) id_aa64isr1_el1.api
374 * 2) id_aa64isr1_el1.apa
375 * 3) id_aa64isr2_el1.apa3
376 */
377 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) {
378 return true;
379 }
380 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) {
381 return true;
382 }
383 if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) {
384 return true;
385 }
386 return false;
387 }
CREATE_FEATURE_SUPPORTED(feat_pauth_lr,is_feat_pauth_lr_present,ENABLE_FEAT_PAUTH_LR)388 CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR)
389
390 /* FEAT_TTST: Small translation tables */
391 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
392 ID_AA64MMFR2_EL1_ST_MASK, 1U,
393 FEAT_ENABLE_ALL_WORLDS)
394
395 /* FEAT_BTI: Branch target identification */
396 CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
397 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI,
398 FEAT_ENABLE_ALL_WORLDS)
399
400 /* FEAT_MTE2: Memory tagging extension */
401 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
402 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2,
403 FEAT_ENABLE_SECURE | FEAT_ENABLE_NS)
404
405 /* FEAT_SSBS: Speculative store bypass safe */
406 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT,
407 ID_AA64PFR1_EL1_SSBS_MASK, 1U,
408 FEAT_ENABLE_ALL_WORLDS)
409
410 /* FEAT_NMI: Non-maskable interrupts */
411 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT,
412 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED,
413 FEAT_ENABLE_ALL_WORLDS)
414
415 /* FEAT_EBEP */
416 CREATE_PERCPU_FEATURE_FUNCS(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT,
417 ID_AA64DFR1_EBEP_MASK, 1U, ENABLE_FEAT_EBEP,
418 FEAT_ENABLE_ALL_WORLDS)
419
420 /* FEAT_SEBEP */
421 CREATE_PERCPU_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT,
422 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED,
423 FEAT_ENABLE_ALL_WORLDS)
424
425 /* FEAT_SEL2: Secure EL2 */
426 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
427 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2,
428 FEAT_ENABLE_ALL_WORLDS)
429
430 /* FEAT_TWED: Delayed trapping of WFE */
431 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
432 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED,
433 FEAT_ENABLE_ALL_WORLDS)
434
435 /* FEAT_FGT: Fine-grained traps */
436 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
437 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT,
438 FEAT_ENABLE_ALL_WORLDS)
439
440 /* FEAT_FGT2: Fine-grained traps extended */
441 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
442 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2,
443 FEAT_ENABLE_ALL_WORLDS)
444
445 /* FEAT_FGWTE3: Fine-grained write traps EL3 */
446 CREATE_FEATURE_FUNCS(feat_fgwte3, id_aa64mmfr4_el1, ID_AA64MMFR4_EL1_FGWTE3_SHIFT,
447 ID_AA64MMFR4_EL1_FGWTE3_MASK, FGWTE3_IMPLEMENTED,
448 ENABLE_FEAT_FGWTE3, FEAT_ENABLE_ALL_WORLDS)
449
450 /* FEAT_ECV: Enhanced Counter Virtualization */
451 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
452 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV,
453 FEAT_ENABLE_ALL_WORLDS)
454 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
455 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH,
456 ENABLE_FEAT_ECV, FEAT_ENABLE_ALL_WORLDS)
457
458 /* FEAT_RNG: Random number generator */
459 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
460 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG,
461 FEAT_ENABLE_ALL_WORLDS)
462
463 /* FEAT_TCR2: Support TCR2_ELx regs */
464 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
465 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2,
466 FEAT_ENABLE_ALL_WORLDS)
467
468 /* FEAT_S2POE */
469 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
470 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE,
471 FEAT_ENABLE_ALL_WORLDS)
472
473 /* FEAT_S1POE */
474 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
475 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE,
476 FEAT_ENABLE_ALL_WORLDS)
477
478 __attribute__((always_inline))
479 static inline bool is_feat_sxpoe_supported(void)
480 {
481 return is_feat_s1poe_supported() || is_feat_s2poe_supported();
482 }
483
484 /* FEAT_S2PIE */
485 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
486 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE,
487 FEAT_ENABLE_ALL_WORLDS)
488
489 /* FEAT_S1PIE */
490 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
491 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE,
492 FEAT_ENABLE_ALL_WORLDS)
493
494 /* FEAT_THE: Translation Hardening Extension */
CREATE_FEATURE_FUNCS(feat_the,id_aa64pfr1_el1,ID_AA64PFR1_EL1_THE_SHIFT,ID_AA64PFR1_EL1_THE_MASK,THE_IMPLEMENTED,ENABLE_FEAT_THE,FEAT_ENABLE_NS)495 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT,
496 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE,
497 FEAT_ENABLE_NS)
498
499 /* FEAT_SCTLR2 */
500 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT,
501 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED,
502 ENABLE_FEAT_SCTLR2,
503 FEAT_ENABLE_NS | FEAT_ENABLE_REALM)
504
505 /* FEAT_D128 */
506 CREATE_FEATURE_FUNCS(feat_d128, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_D128_SHIFT,
507 ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED,
508 ENABLE_FEAT_D128, FEAT_ENABLE_NS | FEAT_ENABLE_REALM)
509
510 /* FEAT_RME_GPC2 */
511 _CREATE_FEATURE_PRESENT(feat_rme_gpc2, id_aa64pfr0_el1,
512 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK,
513 RME_GPC2_IMPLEMENTED)
514
515 /* FEAT_RME_GDI */
516 CREATE_FEATURE_FUNCS(feat_rme_gdi, id_aa64mmfr4_el1,
517 ID_AA64MMFR4_EL1_RME_GDI_SHIFT,
518 ID_AA64MMFR4_EL1_RME_GDI_MASK, RME_GDI_IMPLEMENTED,
519 ENABLE_FEAT_RME_GDI, FEAT_ENABLE_ALL_WORLDS)
520
521 /* FEAT_FPMR */
522 CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT,
523 ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED,
524 ENABLE_FEAT_FPMR, FEAT_ENABLE_NS)
525 /* FEAT_MOPS */
526 CREATE_FEATURE_FUNCS(feat_mops, id_aa64isar2_el1, ID_AA64ISAR2_EL1_MOPS_SHIFT,
527 ID_AA64ISAR2_EL1_MOPS_MASK, MOPS_IMPLEMENTED,
528 ENABLE_FEAT_MOPS, FEAT_ENABLE_ALL_WORLDS)
529
530 __attribute__((always_inline))
531 static inline bool is_feat_sxpie_supported(void)
532 {
533 return is_feat_s1pie_supported() || is_feat_s2pie_supported();
534 }
535
536 /* FEAT_GCS: Guarded Control Stack */
537 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
538 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS,
539 FEAT_ENABLE_ALL_WORLDS)
540
541 /* FEAT_AMU: Activity Monitors Extension */
542 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
543 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU,
544 FEAT_ENABLE_NS)
545
546 /* Auxiliary counters for FEAT_AMU */
547 _CREATE_FEATURE_PRESENT(feat_amu_aux, amcfgr_el0,
548 AMCFGR_EL0_NCG_SHIFT, AMCFGR_EL0_NCG_MASK, 1U)
549
CREATE_FEATURE_SUPPORTED(feat_amu_aux,is_feat_amu_aux_present,ENABLE_AMU_AUXILIARY_COUNTERS)550 CREATE_FEATURE_SUPPORTED(feat_amu_aux, is_feat_amu_aux_present,
551 ENABLE_AMU_AUXILIARY_COUNTERS)
552
553 /* FEAT_AMUV1P1: AMU Extension v1.1 */
554 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
555 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1,
556 FEAT_ENABLE_NS)
557
558 /*
559 * Return MPAM version:
560 *
561 * 0x00: None Armv8.0 or later
562 * 0x01: v0.1 Armv8.4 or later
563 * 0x10: v1.0 Armv8.2 or later
564 * 0x11: v1.1 Armv8.4 or later
565 *
566 */
567 __attribute__((always_inline))
568 static inline bool is_feat_mpam_present(void)
569 {
570 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
571 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
572 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT)
573 & ID_AA64PFR1_MPAM_FRAC_MASK));
574 return ret;
575 }
576
CREATE_FEATURE_SUPPORTED(feat_mpam,is_feat_mpam_present,ENABLE_FEAT_MPAM)577 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
578
579
580 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31)
581 __attribute__((always_inline))
582 static inline void update_feat_mpam_idreg_field(size_t security_state)
583 {
584 if (SHOULD_ID_FIELD_DISABLE(ENABLE_FEAT_MPAM,
585 FEAT_ENABLE_NS | FEAT_ENABLE_REALM, security_state)) {
586 per_world_context_t *per_world_ctx =
587 &per_world_context[security_state];
588 perworld_idregs_t *perworld_idregs =
589 &(per_world_ctx->idregs);
590
591 perworld_idregs->id_aa64pfr0_el1 &=
592 ~((u_register_t)ID_AA64PFR0_MPAM_MASK
593 << ID_AA64PFR0_MPAM_SHIFT);
594
595 perworld_idregs->id_aa64pfr1_el1 &=
596 ~((u_register_t)ID_AA64PFR1_MPAM_FRAC_MASK
597 << ID_AA64PFR1_MPAM_FRAC_SHIFT);
598 }
599 }
600 #endif
601
602 /* FEAT_MPAM_PE_BW_CTRL: MPAM PE-side bandwidth controls */
603 __attribute__((always_inline))
is_feat_mpam_pe_bw_ctrl_present(void)604 static inline bool is_feat_mpam_pe_bw_ctrl_present(void)
605 {
606 if (is_feat_mpam_present()) {
607 return ((unsigned long long)(read_mpamidr_el1() &
608 MPAMIDR_HAS_BW_CTRL_BIT) != 0U);
609 }
610 return false;
611 }
612
CREATE_FEATURE_SUPPORTED(feat_mpam_pe_bw_ctrl,is_feat_mpam_pe_bw_ctrl_present,ENABLE_FEAT_MPAM_PE_BW_CTRL)613 CREATE_FEATURE_SUPPORTED(feat_mpam_pe_bw_ctrl, is_feat_mpam_pe_bw_ctrl_present,
614 ENABLE_FEAT_MPAM_PE_BW_CTRL)
615
616 /*
617 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of
618 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of
619 * Feat_Debug supported. The value of the field determines feature presence
620 *
621 * 0b0110 - Arm v8.0 debug
622 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions
623 * 0x1000 - FEAT_Debugv8p2 is supported
624 * 0x1001 - FEAT_Debugv8p4 is supported
625 * 0x1010 - FEAT_Debugv8p8 is supported
626 * 0x1011 - FEAT_Debugv8p9 is supported
627 *
628 */
629 CREATE_PERCPU_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1,
630 ID_AA64DFR0_DEBUGVER_SHIFT, ID_AA64DFR0_DEBUGVER_MASK,
631 DEBUGVER_V8P9_IMPLEMENTED, ENABLE_FEAT_DEBUGV8P9,
632 FEAT_ENABLE_NS | FEAT_ENABLE_REALM)
633
634 /* FEAT_HCX: Extended Hypervisor Configuration Register */
635 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
636 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX,
637 FEAT_ENABLE_ALL_WORLDS)
638
639 /* FEAT_RNG_TRAP: Trapping support */
640 CREATE_FEATURE_FUNCS(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
641 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED, ENABLE_FEAT_RNG_TRAP,
642 FEAT_ENABLE_ALL_WORLDS)
643
644 /* Return the RME version, zero if not supported. */
645 _CREATE_FEATURE_PRESENT(feat_rme, id_aa64pfr0_el1,
646 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK, 1U)
647
648 CREATE_FEATURE_SUPPORTED(feat_rme, is_feat_rme_present, ENABLE_RME)
649
650 /* FEAT_SB: Speculation barrier instruction */
651 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT,
652 ID_AA64ISAR1_SB_MASK, 1U,
653 FEAT_ENABLE_ALL_WORLDS)
654
655 /* FEAT_MEC: Memory Encryption Contexts */
656 CREATE_FEATURE_FUNCS(feat_mec, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_MEC_SHIFT,
657 ID_AA64MMFR3_EL1_MEC_MASK, 1U, ENABLE_FEAT_MEC,
658 FEAT_ENABLE_ALL_WORLDS)
659
660 /*
661 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
662 * of id_aa64pfr0_el1 register and can be used to check for below features:
663 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2.
664 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3.
665 * 0b0000 - Feature FEAT_CSV2 is not implemented.
666 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3
667 * are not implemented.
668 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not
669 * implemented.
670 * 0b0011 - Feature FEAT_CSV2_3 is implemented.
671 */
672
673 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
674 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2,
675 FEAT_ENABLE_NS | FEAT_ENABLE_REALM)
676 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
677 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3,
678 FEAT_ENABLE_ALL_WORLDS)
679
680 /* FEAT_SPE: Statistical Profiling Extension */
681 CREATE_PERCPU_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
682 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS,
683 FEAT_ENABLE_ALL_WORLDS)
684
685 /* FEAT_SVE: Scalable Vector Extension */
686 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
687 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS,
688 FEAT_ENABLE_ALL_WORLDS)
689
690 /* FEAT_RAS: Reliability, Accessibility, Serviceability */
691 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT,
692 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS,
693 FEAT_ENABLE_ALL_WORLDS)
694
695 /* FEAT_DIT: Data Independent Timing instructions */
696 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT,
697 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT,
698 FEAT_ENABLE_ALL_WORLDS)
699
700 /* FEAT_SYS_REG_TRACE */
701 CREATE_PERCPU_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
702 ID_AA64DFR0_TRACEVER_SHIFT, ID_AA64DFR0_TRACEVER_MASK,
703 1U, ENABLE_SYS_REG_TRACE_FOR_NS,
704 FEAT_ENABLE_ALL_WORLDS)
705
706 /* FEAT_TRF: TraceFilter */
707 CREATE_PERCPU_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
708 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS,
709 FEAT_ENABLE_ALL_WORLDS)
710
711 /* FEAT_NV2: Enhanced Nested Virtualization */
712 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
713 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS,
714 FEAT_ENABLE_ALL_WORLDS)
715
716 /* FEAT_BRBE: Branch Record Buffer Extension */
717 CREATE_PERCPU_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
718 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS,
719 FEAT_ENABLE_NS | FEAT_ENABLE_REALM)
720
721 /* FEAT_TRBE: Trace Buffer Extension */
722 _CREATE_FEATURE_PRESENT(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
723 ID_AA64DFR0_TRACEBUFFER_MASK, 1U)
724
725 CREATE_FEATURE_SUPPORTED(feat_trbe, is_feat_trbe_present, ENABLE_TRBE_FOR_NS)
726
727 CREATE_PERCPU_IDREG_UPDATE(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
728 ID_AA64DFR0_TRACEBUFFER_MASK,
729 ENABLE_TRBE_FOR_NS && !check_if_trbe_disable_affected_core(),
730 FEAT_ENABLE_NS)
731
732 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */
733 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT,
734 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U,
735 FEAT_ENABLE_ALL_WORLDS)
736
737 /* FEAT_SMEx: Scalar Matrix Extension */
738 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
739 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS,
740 FEAT_ENABLE_ALL_WORLDS)
741
742 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
743 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS,
744 FEAT_ENABLE_ALL_WORLDS)
745
746 /* FEAT_LS64_ACCDATA: Support for 64-byte EL0 stores with status */
747 CREATE_FEATURE_FUNCS(feat_ls64_accdata, id_aa64isar1_el1, ID_AA64ISAR1_LS64_SHIFT,
748 ID_AA64ISAR1_LS64_MASK, LS64_ACCDATA_IMPLEMENTED,
749 ENABLE_FEAT_LS64_ACCDATA, FEAT_ENABLE_ALL_WORLDS)
750
751 /* FEAT_AIE: Memory Attribute Index Enhancement */
752 CREATE_FEATURE_FUNCS(feat_aie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_AIE_SHIFT,
753 ID_AA64MMFR3_EL1_AIE_MASK, 1U, ENABLE_FEAT_AIE,
754 FEAT_ENABLE_NS)
755
756 /* FEAT_PFAR: Physical Fault Address Register Extension */
757 CREATE_FEATURE_FUNCS(feat_pfar, id_aa64pfr1_el1, ID_AA64PFR1_EL1_PFAR_SHIFT,
758 ID_AA64PFR1_EL1_PFAR_MASK, 1U, ENABLE_FEAT_PFAR,
759 FEAT_ENABLE_NS)
760
761 /* FEAT_IDTE3: Trapping lower EL ID Register access to EL3 */
762 CREATE_FEATURE_FUNCS(feat_idte3, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_IDS_SHIFT,
763 ID_AA64MMFR2_EL1_IDS_MASK, 2U, ENABLE_FEAT_IDTE3,
764 FEAT_ENABLE_ALL_WORLDS)
765
766 /* FEAT_LSE: Atomic instructions */
767 CREATE_FEATURE_FUNCS(feat_lse, id_aa64isar0_el1, ID_AA64ISAR0_ATOMIC_SHIFT,
768 ID_AA64ISAR0_ATOMIC_MASK, 1U, USE_SPINLOCK_CAS,
769 FEAT_ENABLE_ALL_WORLDS)
770
771
772 /*******************************************************************************
773 * Function to get hardware granularity support
774 ******************************************************************************/
775
776 __attribute__((always_inline))
777 static inline bool is_feat_tgran4K_present(void)
778 {
779 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
780 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK);
781 return (tgranx < 8U);
782 }
783
CREATE_FEATURE_PRESENT(feat_tgran16K,id_aa64mmfr0_el1,ID_AA64MMFR0_EL1_TGRAN16_SHIFT,ID_AA64MMFR0_EL1_TGRAN16_MASK,TGRAN16_IMPLEMENTED,FEAT_ENABLE_ALL_WORLDS)784 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
785 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED,
786 FEAT_ENABLE_ALL_WORLDS)
787
788 __attribute__((always_inline))
789 static inline bool is_feat_tgran64K_present(void)
790 {
791 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
792 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK);
793 return (tgranx < 8U);
794 }
795
796 /* FEAT_PMUV3 */
797 _CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT,
798 ID_AA64DFR0_PMUVER_MASK, 1U)
799
800 /* FEAT_MTPMU */
801 __attribute__((always_inline))
is_feat_mtpmu_present(void)802 static inline bool is_feat_mtpmu_present(void)
803 {
804 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
805 ID_AA64DFR0_MTPMU_MASK);
806 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
807 }
808
809 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
810
811 CREATE_PERCPU_IDREG_UPDATE(feat_mtpmu, id_aa64dfr0_el1, ID_AA64DFR0_MTPMU_SHIFT,
812 ID_AA64DFR0_MTPMU_MASK, DISABLE_MTPMU,
813 FEAT_ENABLE_ALL_WORLDS)
814
815 /*************************************************************************
816 * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface
817 * extension).
818 ************************************************************************/
819 CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT,
820 ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE,
821 FEAT_ENABLE_ALL_WORLDS)
822
823 CREATE_FEATURE_FUNCS(feat_cpa2, id_aa64isar3_el1, ID_AA64ISAR3_EL1_CPA_SHIFT,
824 ID_AA64ISAR3_EL1_CPA_MASK, CPA2_IMPLEMENTED,
825 ENABLE_FEAT_CPA2, FEAT_ENABLE_ALL_WORLDS)
826
827 /* FEAT_UINJ: Injection of Undefined Instruction exceptions */
828 CREATE_FEATURE_FUNCS(feat_uinj, id_aa64pfr2_el1, ID_AA64PFR2_EL1_UINJ_SHIFT,
829 ID_AA64PFR2_EL1_UINJ_MASK, UINJ_IMPLEMENTED,
830 ENABLE_FEAT_UINJ, FEAT_ENABLE_ALL_WORLDS)
831 #endif /* ARCH_FEATURES_H */
832