1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VDPP2_H__ 7 #define __VDPP2_H__ 8 9 #include "vdpp2_reg.h" 10 #include "vdpp_common.h" 11 12 /* vdpp log marco */ 13 #define VDPP2_DBG_TRACE (0x00000001) 14 #define VDPP2_DBG_INT (0x00000002) 15 #define VDPP2_DBG_CHECK (0x00000004) 16 17 extern RK_U32 vdpp2_debug; 18 19 #define VDPP2_DBG(level, fmt, ...)\ 20 do {\ 21 if (level & vdpp2_debug)\ 22 { mpp_log(fmt, ## __VA_ARGS__); }\ 23 } while (0) 24 25 typedef struct ShpParams_t { 26 RK_S32 sharp_enable; 27 RK_S32 sharp_coloradj_bypass_en; 28 29 RK_S32 lti_h_enable; 30 RK_S32 lti_h_radius; 31 RK_S32 lti_h_slope; 32 RK_S32 lti_h_thresold; 33 RK_S32 lti_h_gain; 34 RK_S32 lti_h_noise_thr_pos; 35 RK_S32 lti_h_noise_thr_neg; 36 37 RK_S32 lti_v_enable; 38 RK_S32 lti_v_radius; 39 RK_S32 lti_v_slope; 40 RK_S32 lti_v_thresold; 41 RK_S32 lti_v_gain; 42 RK_S32 lti_v_noise_thr_pos; 43 RK_S32 lti_v_noise_thr_neg; 44 45 RK_S32 cti_h_enable; 46 RK_S32 cti_h_radius; 47 RK_S32 cti_h_slope; 48 RK_S32 cti_h_thresold; 49 RK_S32 cti_h_gain; 50 RK_S32 cti_h_noise_thr_pos; 51 RK_S32 cti_h_noise_thr_neg; 52 53 RK_S32 peaking_enable; 54 RK_S32 peaking_gain; 55 56 RK_S32 peaking_coring_enable; 57 RK_S32 peaking_coring_zero[8]; 58 RK_S32 peaking_coring_thr[8]; 59 RK_S32 peaking_coring_ratio[8]; 60 61 RK_S32 peaking_gain_enable; 62 RK_S32 peaking_gain_pos[8]; 63 RK_S32 peaking_gain_neg[8]; 64 65 RK_S32 peaking_limit_ctrl_enable; 66 RK_S32 peaking_limit_ctrl_pos0[8]; 67 RK_S32 peaking_limit_ctrl_pos1[8]; 68 RK_S32 peaking_limit_ctrl_neg0[8]; 69 RK_S32 peaking_limit_ctrl_neg1[8]; 70 RK_S32 peaking_limit_ctrl_ratio[8]; 71 RK_S32 peaking_limit_ctrl_bnd_pos[8]; 72 RK_S32 peaking_limit_ctrl_bnd_neg[8]; 73 74 RK_S32 peaking_edge_ctrl_enable; 75 RK_S32 peaking_edge_ctrl_non_dir_thr; 76 RK_S32 peaking_edge_ctrl_dir_cmp_ratio; 77 RK_S32 peaking_edge_ctrl_non_dir_wgt_offset; 78 RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio; 79 RK_S32 peaking_edge_ctrl_dir_cnt_thr; 80 RK_S32 peaking_edge_ctrl_dir_cnt_avg; 81 RK_S32 peaking_edge_ctrl_dir_cnt_offset; 82 RK_S32 peaking_edge_ctrl_diag_dir_thr; 83 RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8]; 84 85 RK_S32 peaking_estc_enable; 86 RK_S32 peaking_estc_delta_offset_h; 87 RK_S32 peaking_estc_alpha_over_h; 88 RK_S32 peaking_estc_alpha_under_h; 89 RK_S32 peaking_estc_alpha_over_unlimit_h; 90 RK_S32 peaking_estc_alpha_under_unlimit_h; 91 RK_S32 peaking_estc_delta_offset_v; 92 RK_S32 peaking_estc_alpha_over_v; 93 RK_S32 peaking_estc_alpha_under_v; 94 RK_S32 peaking_estc_alpha_over_unlimit_v; 95 RK_S32 peaking_estc_alpha_under_unlimit_v; 96 RK_S32 peaking_estc_delta_offset_d0; 97 RK_S32 peaking_estc_alpha_over_d0; 98 RK_S32 peaking_estc_alpha_under_d0; 99 RK_S32 peaking_estc_alpha_over_unlimit_d0; 100 RK_S32 peaking_estc_alpha_under_unlimit_d0; 101 RK_S32 peaking_estc_delta_offset_d1; 102 RK_S32 peaking_estc_alpha_over_d1; 103 RK_S32 peaking_estc_alpha_under_d1; 104 RK_S32 peaking_estc_alpha_over_unlimit_d1; 105 RK_S32 peaking_estc_alpha_under_unlimit_d1; 106 RK_S32 peaking_estc_delta_offset_non; 107 RK_S32 peaking_estc_alpha_over_non; 108 RK_S32 peaking_estc_alpha_under_non; 109 RK_S32 peaking_estc_alpha_over_unlimit_non; 110 RK_S32 peaking_estc_alpha_under_unlimit_non; 111 RK_S32 peaking_filter_cfg_diag_enh_coef; 112 113 RK_S32 peaking_filt_core_H0[6]; 114 RK_S32 peaking_filt_core_H1[6]; 115 RK_S32 peaking_filt_core_H2[6]; 116 RK_S32 peaking_filt_core_H3[6]; 117 RK_S32 peaking_filt_core_V0[3]; 118 RK_S32 peaking_filt_core_V1[3]; 119 RK_S32 peaking_filt_core_V2[3]; 120 RK_S32 peaking_filt_core_USM[3]; 121 122 RK_S32 shootctrl_enable; 123 RK_S32 shootctrl_filter_radius; 124 RK_S32 shootctrl_delta_offset; 125 RK_S32 shootctrl_alpha_over; 126 RK_S32 shootctrl_alpha_under; 127 RK_S32 shootctrl_alpha_over_unlimit; 128 RK_S32 shootctrl_alpha_under_unlimit; 129 130 RK_S32 global_gain_enable; 131 RK_S32 global_gain_lum_mode; 132 RK_S32 global_gain_lum_grd[6]; 133 RK_S32 global_gain_lum_val[6]; 134 RK_S32 global_gain_adp_grd[6]; 135 RK_S32 global_gain_adp_val[6]; 136 RK_S32 global_gain_var_grd[6]; 137 RK_S32 global_gain_var_val[6]; 138 139 RK_S32 color_ctrl_enable; 140 141 RK_S32 color_ctrl_p0_scaling_coef; 142 RK_S32 color_ctrl_p0_point_u; 143 RK_S32 color_ctrl_p0_point_v; 144 RK_S32 color_ctrl_p0_roll_tab[16]; 145 146 RK_S32 color_ctrl_p1_scaling_coef; 147 RK_S32 color_ctrl_p1_point_u; 148 RK_S32 color_ctrl_p1_point_v; 149 RK_S32 color_ctrl_p1_roll_tab[16]; 150 151 RK_S32 color_ctrl_p2_scaling_coef; 152 RK_S32 color_ctrl_p2_point_u; 153 RK_S32 color_ctrl_p2_point_v; 154 RK_S32 color_ctrl_p2_roll_tab[16]; 155 156 RK_S32 color_ctrl_p3_scaling_coef; 157 RK_S32 color_ctrl_p3_point_u; 158 RK_S32 color_ctrl_p3_point_v; 159 RK_S32 color_ctrl_p3_roll_tab[16]; 160 161 RK_S32 tex_adj_enable; 162 RK_S32 tex_adj_y_mode_select; 163 RK_S32 tex_adj_mode_select; 164 RK_S32 tex_adj_grd[6]; 165 RK_S32 tex_adj_val[6]; 166 } ShpParams; 167 168 typedef struct EsParams_t { 169 RK_U32 es_bEnabledES; 170 RK_U32 es_iAngleDelta; 171 RK_U32 es_iAngleDeltaExtra; 172 RK_U32 es_iGradNoDirTh; 173 RK_U32 es_iGradFlatTh; 174 RK_U32 es_iWgtGain; 175 RK_U32 es_iWgtDecay; 176 RK_U32 es_iLowConfTh; 177 RK_U32 es_iLowConfRatio; 178 RK_U32 es_iConfCntTh; 179 RK_U32 es_iWgtLocalTh; 180 RK_U32 es_iK1; 181 RK_U32 es_iK2; 182 RK_U32 es_iDeltaLimit; 183 RK_U32 es_iDiff2conf_lut_x[9]; 184 RK_U32 es_iDiff2conf_lut_y[9]; 185 RK_U32 es_bEndpointCheckEnable; 186 RK_U32 es_tan_hi_th; 187 RK_U32 es_tan_lo_th; 188 } EsParams; 189 190 struct vdpp2_params { 191 RK_U32 src_fmt; 192 RK_U32 src_yuv_swap; 193 RK_U32 dst_fmt; 194 RK_U32 dst_yuv_swap; 195 RK_U32 src_width; 196 RK_U32 src_height; 197 RK_U32 src_width_vir; 198 RK_U32 src_height_vir; 199 RK_U32 dst_width; 200 RK_U32 dst_height; 201 RK_U32 dst_width_vir; 202 RK_U32 dst_height_vir; 203 RK_U32 yuv_out_diff; 204 RK_U32 dst_c_width; 205 RK_U32 dst_c_height; 206 RK_U32 dst_c_width_vir; 207 RK_U32 dst_c_height_vir; 208 RK_U32 working_mode; // 2 - VDPP, 3 - DCI HIST 209 210 struct vdpp_addr src; // src frame 211 struct vdpp_addr dst; // dst frame 212 struct vdpp_addr dst_c; // dst chroma 213 214 RK_S32 hist; // dci hist fd 215 216 struct dmsr_params dmsr_params; 217 struct zme_params zme_params; 218 /* vdpp2 new feature */ 219 EsParams es_params; 220 ShpParams shp_params; 221 222 RK_U32 hist_cnt_en; 223 RK_U32 dci_hsd_mode; 224 RK_U32 dci_vsd_mode; 225 RK_U32 dci_yrgb_gather_num; 226 RK_U32 dci_yrgb_gather_en; 227 RK_S32 dci_format; 228 RK_S32 dci_alpha_swap; 229 RK_S32 dci_rbuv_swap; 230 RK_S32 dci_csc_range; 231 }; 232 233 struct vdpp2_api_ctx { 234 RK_S32 fd; 235 struct vdpp2_params params; 236 struct vdpp2_reg reg; 237 struct dmsr_reg dmsr; 238 struct zme_reg zme; 239 }; 240 241 #ifdef __cplusplus 242 extern "C" { 243 #endif 244 245 MPP_RET vdpp2_init(VdppCtx *ictx); 246 MPP_RET vdpp2_deinit(VdppCtx ictx); 247 MPP_RET vdpp2_control(VdppCtx ictx, VdppCmd cmd, void *iparam); 248 RK_S32 vdpp2_check_cap(VdppCtx ictx); 249 250 #ifdef __cplusplus 251 } 252 #endif 253 254 #endif 255