1 // SPDX-License-Identifier: GPL-2.0
2 /********************************************************************************
3 *
4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
5 * Module : video_auto_detect.c
6 * Description :
7 * Author :
8 * Date :
9 * Version : Version 1.0
10 *
11 ********************************************************************************
12 * History :
13 *
14 *
15 ********************************************************************************/
16 #include <linux/string.h>
17 #include <linux/delay.h>
18
19 #include "jaguar1_common.h"
20 #include "jaguar1_video_eq.h"
21 #include "jaguar1_cableA_video_eq_table.h"
22 #include "jaguar1_reg_set_def.h"
23 #include "jaguar1_video.h"
24
25 //extern unsigned int jaguar1_i2c_addr[4];
26
27
NC_VD_EQ_FindFormatDef(NC_VIVO_CH_FORMATDEF format_standard,NC_ANALOG_INPUT analog_input)28 static NC_JAGUAR1_EQ NC_VD_EQ_FindFormatDef( NC_VIVO_CH_FORMATDEF format_standard, NC_ANALOG_INPUT analog_input )
29 {
30 int ii;
31
32 for(ii=0;ii<NC_EQ_SETTING_FMT_MAX;ii++)
33 {
34 _jaguar1_video_eq_value_table_s *pFmt = &equalizer_value_fmtdef_cableA[ ii ];
35
36 if( pFmt->video_fmt == format_standard )
37 if( pFmt->analog_input == analog_input )
38 return ii;
39 }
40
41 printk("NC_VD_EQ_FindFormatDef UNKNOWN format!!!\n");
42
43 return NC_EQ_SETTING_FMT_UNKNOWN;
44 }
45
__eq_base_set_value(video_equalizer_info_s * pvin_eq_set,video_equalizer_base_s * pbase)46 static void __eq_base_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_base_s *pbase )
47 {
48 unsigned char ch = pvin_eq_set->Ch;
49 unsigned char dist = pvin_eq_set->stage;
50
51 REG_SET_5x65_0_8_EQ_BYPASS( ch, pbase->eq_bypass[dist] );
52 REG_SET_5x58_0_8_EQ_BAND_SEL( ch, pbase->eq_band_sel[dist] );
53 REG_SET_5x5C_0_8_EQ_GAIN_SEL( ch, pbase->eq_gain_sel[dist] );
54 REG_SET_Ax3D_0_8_EQ_DEQ_A_ON( ch, pbase->deq_a_on[dist] );
55 REG_SET_Ax3C_0_8_EQ_DEQ_A_SEL( ch, pbase->deq_a_sel[dist] );
56
57 }
58
__eq_coeff_set_value(video_equalizer_info_s * pvin_eq_set,video_equalizer_coeff_s * pcoeff)59 static void __eq_coeff_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_coeff_s *pcoeff )
60 {
61
62 unsigned char ch = pvin_eq_set->Ch;
63 unsigned char dist = pvin_eq_set->stage;
64
65 REG_SET_Ax30_0_8_EQ_DEQ_A_01( ch, pcoeff->deqA_01[dist] );
66 REG_SET_Ax31_0_8_EQ_DEQ_A_02( ch, pcoeff->deqA_02[dist] );
67 REG_SET_Ax32_0_8_EQ_DEQ_A_03( ch, pcoeff->deqA_03[dist] );
68 REG_SET_Ax33_0_8_EQ_DEQ_A_04( ch, pcoeff->deqA_04[dist] );
69 REG_SET_Ax34_0_8_EQ_DEQ_A_05( ch, pcoeff->deqA_05[dist] );
70 REG_SET_Ax35_0_8_EQ_DEQ_A_06( ch, pcoeff->deqA_06[dist] );
71 REG_SET_Ax36_0_8_EQ_DEQ_A_07( ch, pcoeff->deqA_07[dist] );
72 REG_SET_Ax37_0_8_EQ_DEQ_A_08( ch, pcoeff->deqA_08[dist] );
73 REG_SET_Ax38_0_8_EQ_DEQ_A_09( ch, pcoeff->deqA_09[dist] );
74 REG_SET_Ax39_0_8_EQ_DEQ_A_10( ch, pcoeff->deqA_10[dist] );
75 REG_SET_Ax3A_0_8_EQ_DEQ_A_11( ch, pcoeff->deqA_11[dist] );
76 REG_SET_Ax3B_0_8_EQ_DEQ_A_12( ch, pcoeff->deqA_12[dist] );
77
78 }
79
__eq_color_set_value(video_equalizer_info_s * pvin_eq_set,video_equalizer_color_s * pcolor)80 static void __eq_color_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_color_s *pcolor )
81 {
82 unsigned char ch = pvin_eq_set->Ch;
83 unsigned char dist = pvin_eq_set->stage;
84
85 REG_SET_0x24_0_8_EQ_COLOR_CONTRAST( ch, pcolor->contrast[dist] );
86 REG_SET_0x30_0_8_EQ_COLOR_H_PEAKING_1( ch, pcolor->y_peaking_mode[dist] );
87 REG_SET_0x34_0_8_EQ_COLOR_H_PEAKING_2( ch, pcolor->y_fir_mode[dist] );
88
89
90 REG_SET_5x31_0_8_EQ_COLOR_C_FILTER( ch, pcolor->c_filter[dist] );
91
92
93 REG_SET_0x5c_0_8_EQ_PAL_CM_OFF( ch, pcolor->pal_cm_off[dist] );
94
95 REG_SET_0x40_0_8_EQ_COLOR_HUE( ch, pcolor->hue[dist] );
96 REG_SET_0x44_0_8_EQ_COLOR_U_GAIN( ch, pcolor->u_gain[dist] );
97 REG_SET_0x48_0_8_EQ_COLOR_V_GAIN( ch, pcolor->v_gain[dist] );
98 REG_SET_0x4C_0_8_EQ_COLOR_U_OFFSET( ch, pcolor->u_offset[dist] );
99 REG_SET_0x50_0_8_EQ_COLOR_V_OFFSET( ch, pcolor->v_offset[dist] );
100 REG_SET_0x28_0_8_EQ_COLOR_BLACK_LEVEL( ch, pcolor->black_level[dist] );
101
102 REG_SET_5x27_0_8_EQ_COLOR_ACC_REF( ch, pcolor->acc_ref[dist] );
103 REG_SET_5x28_0_8_EQ_COLOR_CTI_DELAY( ch, pcolor->cti_delay[dist] );
104 REG_SET_5x2b_0_8_EQ_COLOR_SUB_SATURATION( ch, pcolor->saturation_b[dist] );
105 REG_SET_5x24_0_8_EQ_COLOR_BURST_DEC_A( ch, pcolor->burst_dec_a[dist] );
106 REG_SET_5x5F_0_8_EQ_COLOR_BURST_DEC_B( ch, pcolor->burst_dec_b[dist] );
107 REG_SET_5xD1_0_8_EQ_COLOR_BURST_DEC_C( ch, pcolor->burst_dec_c[dist] );
108 REG_SET_5xD5_0_8_EQ_COLOR_C_OPTION( ch, pcolor->c_option[dist] );
109 REG_SET_Ax25_0_8_EQ_COLOR_Y_FILTER_B( ch, pcolor->y_filter_b[dist] );
110 REG_SET_Ax27_0_8_EQ_COLOR_Y_FILTER_B_SEL( ch, pcolor->y_filter_b_sel[dist] );
111
112 }
113
__eq_timing_a_set_value(video_equalizer_info_s * pvin_eq_set,video_equalizer_timing_a_s * ptiming_a)114 static void __eq_timing_a_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_timing_a_s *ptiming_a )
115 {
116 unsigned char ch = pvin_eq_set->Ch;
117 unsigned char dist = pvin_eq_set->stage;
118
119 REG_SET_0x68_0_8_EQ_TIMING_A_H_DELAY_A(ch, ptiming_a->h_delay_a[dist] );
120 REG_SET_5x38_0_8_EQ_TIMING_A_H_DELAY_B(ch, ptiming_a->h_delay_b[dist] );
121 REG_SET_0x6C_0_4_EQ_TIMING_A_H_DELAY_C(ch, ptiming_a->h_delay_c[dist] );
122
123 REG_SET_0x64_0_8_EQ_TIMING_A_Y_DELAY(ch , ptiming_a->y_delay[dist] );
124
125 }
126
__eq_clk_set_value(video_equalizer_info_s * pvin_eq_set,video_equalizer_clk_s * pclk)127 static void __eq_clk_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_clk_s *pclk )
128 {
129 unsigned char ch = pvin_eq_set->Ch;
130 unsigned char dist = pvin_eq_set->stage;
131
132 REG_SET_1x84_0_8_EQ_CLOCK_ADC_CLK( ch, pclk->clk_adc[dist] );
133 REG_SET_1x88_0_8_EQ_CLOCK_PRE_CLK( ch, pclk->clk_adc_pre[dist] );
134 REG_SET_1x8C_0_8_EQ_CLOCK_POST_CLK( ch, pclk->clk_adc_post[dist] );
135
136 }
__eq_timing_b_set_value(video_equalizer_info_s * pvin_eq_set,video_equalizer_timing_b_s * ptiming_b)137 static void __eq_timing_b_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_timing_b_s *ptiming_b )
138 {
139 unsigned char ch = pvin_eq_set->Ch;
140 unsigned char dist = pvin_eq_set->stage;
141
142 REG_SET_9x96_0_8_EQ_TIMING_B_HSCALER_1( ch, ptiming_b->h_scaler1[dist] );
143 REG_SET_9x97_0_8_EQ_TIMING_B_HSCALER_2( ch, ptiming_b->h_scaler2[dist] );
144 REG_SET_9x98_0_8_EQ_TIMING_B_HSCALER_3( ch, ptiming_b->h_scaler3[dist] );
145 REG_SET_9x99_0_8_EQ_TIMING_B_HSCALER_4( ch, ptiming_b->h_scaler4[dist] );
146 REG_SET_9x9A_0_8_EQ_TIMING_B_HSCALER_5( ch, ptiming_b->h_scaler5[dist] );
147 REG_SET_9x9B_0_8_EQ_TIMING_B_HSCALER_6( ch, ptiming_b->h_scaler6[dist] );
148 REG_SET_9x9C_0_8_EQ_TIMING_B_HSCALER_7( ch, ptiming_b->h_scaler7[dist] );
149 REG_SET_9x9D_0_8_EQ_TIMING_B_HSCALER_8( ch, ptiming_b->h_scaler8[dist] );
150 REG_SET_9x9E_0_8_EQ_TIMING_B_HSCALER_9( ch, ptiming_b->h_scaler9[dist] );
151 REG_SET_9x40_0_8_EQ_TIMING_B_PN_AUTO( ch, ptiming_b->pn_auto[dist] );
152 REG_SET_5x90_0_8_EQ_TIMINING_B_COMB_MODE( ch, ptiming_b->comb_mode[dist] );
153 REG_SET_5xB9_0_8_EQ_TIMING_B_HPLL_OP_A( ch, ptiming_b->h_pll_op_a[dist] );
154 REG_SET_5x57_0_8_EQ_TIMING_B_MEM_PATH( ch, ptiming_b->mem_path[dist] );
155 REG_SET_5x25_0_8_EQ_TIMING_B_FSC_LOCK_SPD( ch, ptiming_b->fsc_lock_speed[dist] );
156
157 REG_SET_0x04_0_8_EQ_TIMING_B_SD_MD( ch, ptiming_b->sd_mode[dist] );
158 REG_SET_0x08_0_8_EQ_TIMING_B_AHD_MD( ch, ptiming_b->ahd_mode[dist] );
159 REG_SET_0x0C_0_8_EQ_TIMING_B_SPECIAL_MD( ch, ptiming_b->spl_mode[dist] );
160 REG_SET_0x78_0_8_EQ_TIMING_B_VBLK_END( ch, ptiming_b->vblk_end[dist] );
161
162 REG_SET_5x1D_0_8_EQ_AFE_G_SEL( ch, ptiming_b->afe_g_sel[dist] );
163 REG_SET_5x01_0_8_EQ_AFE_CTR_CLP( ch, ptiming_b->afe_ctr_clp[dist] );
164 REG_SET_5x05_0_8_EQ_D_AGC_OPTION( ch, ptiming_b->d_agc_option[dist] );
165
166 }
167
video_input_eq_val_set(video_equalizer_info_s * pvin_eq_set)168 void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set)
169 {
170 NC_JAGUAR1_EQ eq_fmt;
171 unsigned char ch = pvin_eq_set->Ch;
172 int fmt = pvin_eq_set->FmtDef;
173 int input = pvin_eq_set->Input;
174 int cable = pvin_eq_set->Cable;
175 /* int stage = pvin_eq_set->stage; */
176 _jaguar1_video_eq_value_table_s eq_value;
177
178 // printk("[drv_eq]ch%d >> fmt(%d) cable(%d) stage(%d) input(%d)\n", ch, fmt, cable, stage, input);
179 eq_fmt = NC_VD_EQ_FindFormatDef( fmt, input );
180
181 if( cable == CABLE_A )
182 eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
183 else if( cable == CABLE_B )
184 eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
185 else if( cable == CABLE_C )
186 eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
187 else if( cable == CABLE_D )
188 eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
189 else
190 eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
191
192 if( eq_value.name == NULL )
193 {
194 printk("[drv_eq]Error - Unknown EQ Table!!\n");
195 return;
196 }
197 else
198 {
199 /* set_eq_value */
200 __eq_base_set_value( pvin_eq_set, &eq_value.eq_base );
201 __eq_coeff_set_value( pvin_eq_set, &eq_value.eq_coeff );
202 __eq_color_set_value( pvin_eq_set, &eq_value.eq_color);
203 __eq_timing_a_set_value( pvin_eq_set, &eq_value.eq_timing_a );
204 __eq_clk_set_value( pvin_eq_set, &eq_value.eq_clk );
205 __eq_timing_b_set_value( pvin_eq_set, &eq_value.eq_timing_b );
206
207 printk("[drv_eq]ch::%d >>> fmt::%s\n", ch, eq_value.name);
208 }
209 }
210
211
video_input_eq_cable_set(video_equalizer_info_s * pvin_eq_set)212 void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set)
213 {
214 unsigned char ch = pvin_eq_set->Ch;
215 int cable = pvin_eq_set->Cable;
216
217 printk("[DRV]video_input_eq_cable_set::ch(%d) cable(%d)\n", ch, cable );
218 }
219
video_input_eq_analog_input_set(video_equalizer_info_s * pvin_eq_set)220 void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set)
221 {
222 unsigned char ch = pvin_eq_set->Ch;
223 int input = pvin_eq_set->Input;
224
225 REG_SET_0x18_0_8_EX_CBAR_ON( ch, 0x13 );
226
227 if( input == DIFFERENTIAL )
228 {
229 REG_SET_5x00_0_8_CMP( ch, 0xd0 );
230 REG_SET_5x01_0_8_CML( ch, 0x2c );
231 REG_SET_5x1D_0_8_AFE( ch, 0x8c );
232 REG_SET_5x92_0_8_PWM( ch, 0x00 );
233 }
234 else if( input == SINGLE_ENDED )
235 {
236 REG_SET_5x00_0_8_CMP( ch, 0xd0 );
237 REG_SET_5x01_0_8_CML( ch, 0xa2 );
238 // REG_SET_5x1D_0_8_AFE( ch, 0x00 );
239 REG_SET_5x92_0_8_PWM( ch, 0x00 );
240 }
241 else
242 {
243 printk("Jaguar1 Analog Input Setting Fail !!!\n");
244 }
245
246 printk("[DRV]video_input_eq_analog_input_set::ch(%d) input(%d)\n", ch, input );
247 }
248
249