1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/video/rockchip/video/vehicle_cif.c
4 *
5 * mipi_dphy/csi_host/vicap driver for vehicle
6 *
7 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
8 * Authors:
9 * Jianwei Fan <jianwei.fan@rock-chips.com>
10 *
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/kernel.h>
18 #include <linux/time.h>
19 #include <linux/platform_device.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/fb.h>
23 #include <linux/clk.h>
24 #include <linux/clkdev.h>
25 #include <linux/of_gpio.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/reset.h>
29
30 #include "vehicle-csi2-dphy-common.h"
31 #include "vehicle_cif.h"
32 #include "vehicle_flinger.h"
33 #include "vehicle_main.h"
34
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <media/v4l2-mediabus.h>
38 #include <linux/delay.h>
39 #include <linux/pm_runtime.h>
40 #include <dt-bindings/soc/rockchip-system-status.h>
41 #include <soc/rockchip/rockchip-system-status.h>
42 #include <linux/phy/phy.h>
43 #include <linux/uaccess.h>
44 #include <linux/bits.h>
45 #include "vehicle_samsung_dcphy_common.h"
46
47 #define CIF_DG VEHICLE_DG
48 #define CIF_ERR VEHICLE_DGERR
49
50 static struct vehicle_cif *g_cif;
51
52 #define write_reg(base, addr, val) \
53 writel(val, (addr) + (base))
54 #define read_reg(base, addr) \
55 readl((addr) + (base))
56
57 #define vehicle_write_csihost_reg(base, addr, val) write_reg(base, addr, val)
58 #define vehicle_read_csihost_reg(base, addr) read_reg(base, addr)
59
60 //define cif clk and rst
61 static const char * const rk3568_cif_clks[] = {
62 "aclk_cif",
63 "hclk_cif",
64 "dclk_cif",
65 "iclk_cif_g",
66 };
67
68 static const char * const rk3568_cif_rsts[] = {
69 "rst_cif_a",
70 "rst_cif_h",
71 "rst_cif_d",
72 "rst_cif_p",
73 "rst_cif_i",
74 };
75
76 static const char * const rk3588_cif_clks[] = {
77 "aclk_cif",
78 "hclk_cif",
79 "dclk_cif",
80 };
81
82 static const char * const rk3588_cif_rsts[] = {
83 "rst_cif_a",
84 "rst_cif_h",
85 "rst_cif_d",
86 };
87
88 static const char * const rk3562_cif_clks[] = {
89 "aclk_cif",
90 "hclk_cif",
91 "dclk_cif",
92 "csirx0_data",
93 "csirx1_data",
94 "csirx2_data",
95 "csirx3_data",
96 };
97
98 static const char * const rk3562_cif_rsts[] = {
99 "rst_cif_a",
100 "rst_cif_h",
101 "rst_cif_d",
102 "rst_cif_i0",
103 "rst_cif_i1",
104 "rst_cif_i2",
105 "rst_cif_i3",
106 };
107
108 //define dphy and csi clks/rst
109 static struct clk_bulk_data rk3568_csi2_dphy_hw_clks[] = {
110 { .id = "pclk" },
111 };
112
113 static struct clk_bulk_data rk3568_csi2_clks[] = {
114 { .id = "pclk_csi2host" },
115 };
116
117 static const char * const rk3568_csi2_rsts[] = {
118 "srst_csihost_p",
119 };
120
121 static struct clk_bulk_data rk3588_csi2_dphy_hw_clks[] = {
122 { .id = "pclk" },
123 };
124
125 static const char * const rk3588_csi2_dphy_hw_rsts[] = {
126 "srst_csiphy",
127 "srst_p_csiphy",
128 };
129
130 static struct clk_bulk_data rk3588_csi2_clks[] = {
131 { .id = "pclk_csi2host" },
132 };
133
134 static struct clk_bulk_data rk3588_csi2_dcphy_clks[] = {
135 { .id = "pclk_csi2host" },
136 { .id = "iclk_csi2host" },
137 };
138
139 static const char * const rk3588_csi2_rsts[] = {
140 "srst_csihost_p",
141 "srst_csihost_vicap",
142 };
143
144 static struct clk_bulk_data rk3562_csi2_dphy_hw_clks[] = {
145 { .id = "pclk" },
146 };
147
148 static const char * const rk3562_csi2_dphy_hw_rsts[] = {
149 "srst_p_csiphy",
150 };
151
152 static struct clk_bulk_data rk3562_csi2_clks[] = {
153 { .id = "pclk_csi2host" },
154 };
155
156 static const char * const rk3562_csi2_rsts[] = {
157 "srst_csihost_p",
158 };
159
160 //define cif regs
161 static const struct vehicle_cif_reg rk3568_cif_regs[] = {
162 [CIF_REG_DVP_CTRL] = CIF_REG_NAME(CIF_CTRL, "CIF_REG_DVP_CTRL"),
163 [CIF_REG_DVP_INTEN] = CIF_REG_NAME(CIF_INTEN, "CIF_REG_DVP_INTEN"),
164 [CIF_REG_DVP_INTSTAT] = CIF_REG_NAME(CIF_INTSTAT, "CIF_REG_DVP_INTSTAT"),
165 [CIF_REG_DVP_FOR] = CIF_REG_NAME(CIF_FOR, "CIF_REG_DVP_FOR"),
166 [CIF_REG_DVP_MULTI_ID] = CIF_REG_NAME(CIF_MULTI_ID, "CIF_REG_DVP_MULTI_ID"),
167 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG_NAME(CIF_FRM0_ADDR_Y, "CIF_REG_DVP_FRM0_ADDR_Y"),
168 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG_NAME(CIF_FRM0_ADDR_UV, "CIF_REG_DVP_FRM0_ADDR_UV"),
169 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG_NAME(CIF_FRM1_ADDR_Y, "CIF_REG_DVP_FRM1_ADDR_Y"),
170 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG_NAME(CIF_FRM1_ADDR_UV, "CIF_REG_DVP_FRM1_ADDR_UV"),
171 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG_NAME(CIF_VIR_LINE_WIDTH,
172 "CIF_REG_DVP_VIR_LINE_WIDTH"),
173 [CIF_REG_DVP_SET_SIZE] = CIF_REG_NAME(CIF_SET_SIZE, "CIF_REG_DVP_SET_SIZE"),
174 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG_NAME(CIF_LINE_INT_NUM, "CIF_REG_DVP_LINE_INT_NUM"),
175 [CIF_REG_DVP_LINE_CNT] = CIF_REG_NAME(CIF_LINE_CNT, "CIF_REG_DVP_LINE_CNT"),
176 [CIF_REG_DVP_CROP] = CIF_REG_NAME(RV1126_CIF_CROP, "CIF_REG_DVP_CROP"),
177 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG_NAME(RK3568_CIF_FIFO_ENTRY, "CIF_REG_DVP_FIFO_ENTRY"),
178 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG_NAME(RV1126_CIF_FRAME_STATUS,
179 "CIF_REG_DVP_FRAME_STATUS"),
180 [CIF_REG_DVP_CUR_DST] = CIF_REG_NAME(RV1126_CIF_CUR_DST, "CIF_REG_DVP_CUR_DST"),
181 [CIF_REG_DVP_LAST_LINE] = CIF_REG_NAME(RV1126_CIF_LAST_LINE, "CIF_REG_DVP_LAST_LINE"),
182 [CIF_REG_DVP_LAST_PIX] = CIF_REG_NAME(RV1126_CIF_LAST_PIX, "CIF_REG_DVP_LAST_PIX"),
183 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG_NAME(CIF_FRM0_ADDR_Y_ID1,
184 "CIF_REG_DVP_FRM0_ADDR_Y_ID1"),
185 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG_NAME(CIF_FRM0_ADDR_UV_ID1,
186 "CIF_REG_DVP_FRM0_ADDR_UV_ID1"),
187 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG_NAME(CIF_FRM1_ADDR_Y_ID1,
188 "CIF_REG_DVP_FRM1_ADDR_Y_ID1"),
189 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG_NAME(CIF_FRM1_ADDR_UV_ID1,
190 "CIF_REG_DVP_FRM1_ADDR_UV_ID1"),
191 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG_NAME(CIF_FRM0_ADDR_Y_ID2,
192 "CIF_REG_DVP_FRM0_ADDR_Y_ID2"),
193 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG_NAME(CIF_FRM0_ADDR_UV_ID2,
194 "CIF_REG_DVP_FRM0_ADDR_UV_ID2"),
195 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG_NAME(CIF_FRM1_ADDR_Y_ID2,
196 "CIF_REG_DVP_FRM1_ADDR_Y_ID2"),
197 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG_NAME(CIF_FRM1_ADDR_UV_ID2,
198 "CIF_REG_DVP_FRM1_ADDR_UV_ID2"),
199 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG_NAME(CIF_FRM0_ADDR_Y_ID3,
200 "CIF_REG_DVP_FRM0_ADDR_Y_ID3"),
201 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG_NAME(CIF_FRM0_ADDR_UV_ID3,
202 "CIF_REG_DVP_FRM0_ADDR_UV_ID3"),
203 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG_NAME(CIF_FRM1_ADDR_Y_ID3,
204 "CIF_REG_DVP_FRM1_ADDR_Y_ID3"),
205 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG_NAME(CIF_FRM1_ADDR_UV_ID3,
206 "CIF_REG_DVP_FRM1_ADDR_UV_ID3"),
207 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG_NAME(CIF_CSI_ID0_CTRL0,
208 "CIF_REG_MIPI_LVDS_ID0_CTRL0"),
209 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG_NAME(CIF_CSI_ID0_CTRL1,
210 "CIF_REG_MIPI_LVDS_ID0_CTRL1"),
211 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG_NAME(CIF_CSI_ID1_CTRL0,
212 "CIF_REG_MIPI_LVDS_ID1_CTRL0"),
213 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG_NAME(CIF_CSI_ID1_CTRL1,
214 "CIF_REG_MIPI_LVDS_ID1_CTRL1"),
215 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG_NAME(CIF_CSI_ID2_CTRL0,
216 "CIF_REG_MIPI_LVDS_ID2_CTRL0"),
217 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG_NAME(CIF_CSI_ID2_CTRL1,
218 "CIF_REG_MIPI_LVDS_ID2_CTRL1"),
219 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG_NAME(CIF_CSI_ID3_CTRL0,
220 "CIF_REG_MIPI_LVDS_ID3_CTRL0"),
221 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG_NAME(CIF_CSI_ID3_CTRL1,
222 "CIF_REG_MIPI_LVDS_ID3_CTRL1"),
223 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG_NAME(CIF_CSI_MIPI_LVDS_CTRL,
224 "CIF_REG_MIPI_LVDS_CTRL"),
225 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_Y_ID0,
226 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0"),
227 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_Y_ID0,
228 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0"),
229 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_UV_ID0,
230 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0"),
231 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_UV_ID0,
232 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0"),
233 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_Y_ID0,
234 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0"),
235 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_Y_ID0,
236 "CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0"),
237 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_UV_ID0,
238 "CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0"),
239 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_UV_ID0,
240 "CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0"),
241 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_Y_ID1,
242 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1"),
243 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_Y_ID1,
244 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1"),
245 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_UV_ID1,
246 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1"),
247 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_UV_ID1,
248 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1"),
249 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_Y_ID1,
250 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1"),
251 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_Y_ID1,
252 "CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1"),
253 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_UV_ID1,
254 "CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1"),
255 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_UV_ID1,
256 "CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1"),
257 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_Y_ID2,
258 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2"),
259 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_Y_ID2,
260 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2"),
261 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_UV_ID2,
262 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2"),
263 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_UV_ID2,
264 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2"),
265 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_Y_ID2,
266 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2"),
267 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_Y_ID2,
268 "CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2"),
269 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_UV_ID2,
270 "CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2"),
271 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_UV_ID2,
272 "CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2"),
273 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_Y_ID3,
274 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3"),
275 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_Y_ID3,
276 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3"),
277 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG_NAME(CIF_CSI_FRM0_ADDR_UV_ID3,
278 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3"),
279 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG_NAME(CIF_CSI_FRM1_ADDR_UV_ID3,
280 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3"),
281 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_Y_ID3,
282 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3"),
283 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_Y_ID3,
284 "CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3"),
285 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG_NAME(CIF_CSI_FRM0_VLW_UV_ID3,
286 "CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3"),
287 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG_NAME(CIF_CSI_FRM1_VLW_UV_ID3,
288 "CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3"),
289 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG_NAME(CIF_CSI_INTEN, "CIF_REG_MIPI_LVDS_INTEN"),
290 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG_NAME(CIF_CSI_INTSTAT, "CIF_REG_MIPI_LVDS_INTSTAT"),
291 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG_NAME(CIF_CSI_LINE_INT_NUM_ID0_1,
292 "CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1"),
293 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG_NAME(CIF_CSI_LINE_INT_NUM_ID2_3,
294 "CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3"),
295 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG_NAME(CIF_CSI_LINE_CNT_ID0_1,
296 "CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1"),
297 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG_NAME(CIF_CSI_LINE_CNT_ID2_3,
298 "CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3"),
299 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG_NAME(CIF_CSI_ID0_CROP_START,
300 "CIF_REG_MIPI_LVDS_ID0_CROP_START"),
301 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG_NAME(CIF_CSI_ID1_CROP_START,
302 "CIF_REG_MIPI_LVDS_ID1_CROP_START"),
303 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG_NAME(CIF_CSI_ID2_CROP_START,
304 "CIF_REG_MIPI_LVDS_ID2_CROP_START"),
305 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG_NAME(CIF_CSI_ID3_CROP_START,
306 "CIF_REG_MIPI_LVDS_ID3_CROP_START"),
307 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG_NAME(CIF_CSI_FRAME_NUM_VC0,
308 "CIF_REG_MIPI_FRAME_NUM_VC0"),
309 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG_NAME(CIF_CSI_FRAME_NUM_VC1,
310 "CIF_REG_MIPI_FRAME_NUM_VC1"),
311 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG_NAME(CIF_CSI_FRAME_NUM_VC2,
312 "CIF_REG_MIPI_FRAME_NUM_VC2"),
313 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG_NAME(CIF_CSI_FRAME_NUM_VC3,
314 "CIF_REG_MIPI_FRAME_NUM_VC3"),
315 [CIF_REG_Y_STAT_CONTROL] = CIF_REG_NAME(CIF_Y_STAT_CONTROL,
316 "CIF_REG_Y_STAT_CONTROL"),
317 [CIF_REG_Y_STAT_VALUE] = CIF_REG_NAME(CIF_Y_STAT_VALUE, "CIF_REG_Y_STAT_VALUE"),
318 [CIF_REG_MMU_DTE_ADDR] = CIF_REG_NAME(CIF_MMU_DTE_ADDR, "CIF_REG_MMU_DTE_ADDR"),
319 [CIF_REG_MMU_STATUS] = CIF_REG_NAME(CIF_MMU_STATUS, "CIF_REG_MMU_STATUS"),
320 [CIF_REG_MMU_COMMAND] = CIF_REG_NAME(CIF_MMU_COMMAND, "CIF_REG_MMU_COMMAND"),
321 [CIF_REG_MMU_PAGE_FAULT_ADDR] = CIF_REG_NAME(CIF_MMU_PAGE_FAULT_ADDR,
322 "CIF_REG_MMU_PAGE_FAULT_ADDR"),
323 [CIF_REG_MMU_ZAP_ONE_LINE] = CIF_REG_NAME(CIF_MMU_ZAP_ONE_LINE, "CIF_REG_MMU_ZAP_ONE_LINE"),
324 [CIF_REG_MMU_INT_RAWSTAT] = CIF_REG_NAME(CIF_MMU_INT_RAWSTAT, "CIF_REG_MMU_INT_RAWSTAT"),
325 [CIF_REG_MMU_INT_CLEAR] = CIF_REG_NAME(CIF_MMU_INT_CLEAR, "CIF_REG_MMU_INT_CLEAR"),
326 [CIF_REG_MMU_INT_MASK] = CIF_REG_NAME(CIF_MMU_INT_MASK, "CIF_REG_MMU_INT_MASK"),
327 [CIF_REG_MMU_INT_STATUS] = CIF_REG_NAME(CIF_MMU_INT_STATUS, "CIF_REG_MMU_INT_STATUS"),
328 [CIF_REG_MMU_AUTO_GATING] = CIF_REG_NAME(CIF_MMU_AUTO_GATING, "CIF_REG_MMU_AUTO_GATING"),
329 [CIF_REG_GRF_CIFIO_CON] = CIF_REG_NAME(CIF_GRF_VI_CON0, "CIF_REG_GRF_CIFIO_CON"),
330 [CIF_REG_GRF_CIFIO_CON1] = CIF_REG_NAME(CIF_GRF_VI_CON1, "CIF_REG_GRF_CIFIO_CON1"),
331 };
332
333 static const struct vehicle_cif_reg rk3588_cif_regs[] = {
334 [CIF_REG_DVP_CTRL] = CIF_REG_NAME(DVP_CTRL, "CIF_REG_DVP_CTRL"),
335 [CIF_REG_DVP_INTEN] = CIF_REG_NAME(DVP_INTEN, "CIF_REG_DVP_INTEN"),
336 [CIF_REG_DVP_INTSTAT] = CIF_REG_NAME(DVP_INTSTAT, "CIF_REG_DVP_INTSTAT"),
337 [CIF_REG_DVP_FOR] = CIF_REG_NAME(DVP_FOR, "CIF_REG_DVP_FOR"),
338 [CIF_REG_DVP_MULTI_ID] = CIF_REG_NAME(DVP_MULTI_ID, "CIF_REG_DVP_MULTI_ID"),
339 [CIF_REG_DVP_SAV_EAV] = CIF_REG_NAME(DVP_SAV_EAV, "CIF_REG_DVP_SAV_EAV"),
340 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG_NAME(DVP_FRM0_ADDR_Y_ID0, "CIF_REG_DVP_FRM0_ADDR_Y"),
341 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG_NAME(DVP_FRM0_ADDR_UV_ID0, "CIF_REG_DVP_FRM0_ADDR_UV"),
342 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG_NAME(DVP_FRM1_ADDR_Y_ID0, "CIF_REG_DVP_FRM1_ADDR_Y"),
343 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG_NAME(DVP_FRM1_ADDR_UV_ID0, "CIF_REG_DVP_FRM1_ADDR_UV"),
344 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG_NAME(DVP_FRM0_ADDR_Y_ID1,
345 "CIF_REG_DVP_FRM0_ADDR_Y_ID1"),
346 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG_NAME(DVP_FRM0_ADDR_UV_ID1,
347 "CIF_REG_DVP_FRM0_ADDR_UV_ID1"),
348 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG_NAME(DVP_FRM1_ADDR_Y_ID1,
349 "CIF_REG_DVP_FRM1_ADDR_Y_ID1"),
350 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG_NAME(DVP_FRM1_ADDR_UV_ID1,
351 "CIF_REG_DVP_FRM1_ADDR_UV_ID1"),
352 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG_NAME(DVP_FRM0_ADDR_Y_ID2,
353 "CIF_REG_DVP_FRM0_ADDR_Y_ID2"),
354 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG_NAME(DVP_FRM0_ADDR_UV_ID2,
355 "CIF_REG_DVP_FRM0_ADDR_UV_ID2"),
356 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG_NAME(DVP_FRM1_ADDR_Y_ID2,
357 "CIF_REG_DVP_FRM1_ADDR_Y_ID2"),
358 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG_NAME(DVP_FRM1_ADDR_UV_ID2,
359 "CIF_REG_DVP_FRM1_ADDR_UV_ID2"),
360 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG_NAME(DVP_FRM0_ADDR_Y_ID3,
361 "CIF_REG_DVP_FRM0_ADDR_Y_ID3"),
362 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG_NAME(DVP_FRM0_ADDR_UV_ID3,
363 "CIF_REG_DVP_FRM0_ADDR_UV_ID3"),
364 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG_NAME(DVP_FRM1_ADDR_Y_ID3,
365 "CIF_REG_DVP_FRM1_ADDR_Y_ID3"),
366 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG_NAME(DVP_FRM1_ADDR_UV_ID3,
367 "CIF_REG_DVP_FRM1_ADDR_UV_ID3"),
368 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG_NAME(DVP_VIR_LINE_WIDTH,
369 "CIF_REG_DVP_VIR_LINE_WIDTH"),
370 [CIF_REG_DVP_SET_SIZE] = CIF_REG_NAME(DVP_CROP_SIZE, "CIF_REG_DVP_SET_SIZE"),
371 [CIF_REG_DVP_CROP] = CIF_REG_NAME(DVP_CROP, "CIF_REG_DVP_CROP"),
372 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG_NAME(DVP_LINE_INT_NUM_01, "CIF_REG_DVP_LINE_INT_NUM"),
373 [CIF_REG_DVP_LINE_INT_NUM1] = CIF_REG_NAME(DVP_LINE_INT_NUM_23,
374 "CIF_REG_DVP_LINE_INT_NUM1"),
375 [CIF_REG_DVP_LINE_CNT] = CIF_REG_NAME(DVP_LINE_INT_NUM_01, "CIF_REG_DVP_LINE_CNT"),
376 [CIF_REG_DVP_LINE_CNT1] = CIF_REG_NAME(DVP_LINE_INT_NUM_23, "CIF_REG_DVP_LINE_CNT1"),
377 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID0_CTRL0,
378 "CIF_REG_MIPI_LVDS_ID0_CTRL0"),
379 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID0_CTRL1,
380 "CIF_REG_MIPI_LVDS_ID0_CTRL1"),
381 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID1_CTRL0,
382 "CIF_REG_MIPI_LVDS_ID1_CTRL0"),
383 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID1_CTRL1,
384 "CIF_REG_MIPI_LVDS_ID1_CTRL1"),
385 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID2_CTRL0,
386 "CIF_REG_MIPI_LVDS_ID2_CTRL0"),
387 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID2_CTRL1,
388 "CIF_REG_MIPI_LVDS_ID2_CTRL1"),
389 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID3_CTRL0,
390 "CIF_REG_MIPI_LVDS_ID3_CTRL0"),
391 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID3_CTRL1,
392 "CIF_REG_MIPI_LVDS_ID3_CTRL1"),
393 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG_NAME(CSI_MIPI0_CTRL, "CIF_REG_MIPI_LVDS_CTRL"),
394 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID0,
395 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0"),
396 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID0,
397 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0"),
398 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID0,
399 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0"),
400 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID0,
401 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0"),
402 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG_NAME(CSI_MIPI0_VLW_ID0,
403 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0"),
404 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID1,
405 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1"),
406 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID1,
407 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1"),
408 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID1,
409 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1"),
410 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID1,
411 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1"),
412 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG_NAME(CSI_MIPI0_VLW_ID1,
413 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1"),
414 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID2,
415 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2"),
416 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID2,
417 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2"),
418 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID2,
419 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2"),
420 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID2,
421 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2"),
422 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG_NAME(CSI_MIPI0_VLW_ID2,
423 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2"),
424 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID3,
425 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3"),
426 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID3,
427 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3"),
428 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID3,
429 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3"),
430 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID3,
431 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3"),
432 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG_NAME(CSI_MIPI0_VLW_ID3,
433 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3"),
434 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG_NAME(CSI_MIPI0_INTEN, "CIF_REG_MIPI_LVDS_INTEN"),
435 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG_NAME(CSI_MIPI0_INTSTAT, "CIF_REG_MIPI_LVDS_INTSTAT"),
436 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG_NAME(CSI_MIPI0_LINE_INT_NUM_ID0_1,
437 "CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1"),
438 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG_NAME(CSI_MIPI0_LINE_INT_NUM_ID2_3,
439 "CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3"),
440 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG_NAME(CSI_MIPI0_LINE_CNT_ID0_1,
441 "CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1"),
442 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG_NAME(CSI_MIPI0_LINE_CNT_ID2_3,
443 "CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3"),
444 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID0_CROP_START,
445 "CIF_REG_MIPI_LVDS_ID0_CROP_START"),
446 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID1_CROP_START,
447 "CIF_REG_MIPI_LVDS_ID1_CROP_START"),
448 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID2_CROP_START,
449 "CIF_REG_MIPI_LVDS_ID2_CROP_START"),
450 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID3_CROP_START,
451 "CIF_REG_MIPI_LVDS_ID3_CROP_START"),
452 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC0,
453 "CIF_REG_MIPI_FRAME_NUM_VC0"),
454 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC1,
455 "CIF_REG_MIPI_FRAME_NUM_VC1"),
456 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC2,
457 "CIF_REG_MIPI_FRAME_NUM_VC2"),
458 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC3,
459 "CIF_REG_MIPI_FRAME_NUM_VC3"),
460 [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID0,
461 "CIF_REG_MIPI_EFFECT_CODE_ID0"),
462 [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID1,
463 "CIF_REG_MIPI_EFFECT_CODE_ID1"),
464 [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID2,
465 "CIF_REG_MIPI_EFFECT_CODE_ID2"),
466 [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID3,
467 "CIF_REG_MIPI_EFFECT_CODE_ID3"),
468 [CIF_REG_MIPI_ON_PAD] = CIF_REG_NAME(CSI_MIPI0_ON_PAD, "CIF_REG_MIPI_ON_PAD"),
469 [CIF_REG_GLB_CTRL] = CIF_REG_NAME(GLB_CTRL, "CIF_REG_GLB_CTRL"),
470 [CIF_REG_GLB_INTEN] = CIF_REG_NAME(GLB_INTEN, "CIF_REG_GLB_INTEN"),
471 [CIF_REG_GLB_INTST] = CIF_REG_NAME(GLB_INTST, "CIF_REG_GLB_INTST"),
472 [CIF_REG_SCL_CH_CTRL] = CIF_REG_NAME(SCL_CH_CTRL, "CIF_REG_SCL_CH_CTRL"),
473 [CIF_REG_SCL_CTRL] = CIF_REG_NAME(SCL_CTRL, "CIF_REG_SCL_CTRL"),
474 [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG_NAME(SCL_FRM0_ADDR_CH0,
475 "CIF_REG_SCL_FRM0_ADDR_CH0"),
476 [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG_NAME(SCL_FRM1_ADDR_CH0,
477 "CIF_REG_SCL_FRM1_ADDR_CH0"),
478 [CIF_REG_SCL_VLW_CH0] = CIF_REG_NAME(SCL_VLW_CH0, "CIF_REG_SCL_VLW_CH0"),
479 [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG_NAME(SCL_FRM0_ADDR_CH1,
480 "CIF_REG_SCL_FRM0_ADDR_CH1"),
481 [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG_NAME(SCL_FRM1_ADDR_CH1,
482 "CIF_REG_SCL_FRM1_ADDR_CH1"),
483 [CIF_REG_SCL_VLW_CH1] = CIF_REG_NAME(SCL_VLW_CH1, "CIF_REG_SCL_VLW_CH1"),
484 [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG_NAME(SCL_FRM0_ADDR_CH2,
485 "CIF_REG_SCL_FRM0_ADDR_CH2"),
486 [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG_NAME(SCL_FRM1_ADDR_CH2,
487 "CIF_REG_SCL_FRM1_ADDR_CH2"),
488 [CIF_REG_SCL_VLW_CH2] = CIF_REG_NAME(SCL_VLW_CH2, "CIF_REG_SCL_VLW_CH2"),
489 [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG_NAME(SCL_FRM0_ADDR_CH3, "CIF_REG_SCL_FRM0_ADDR_CH3"),
490 [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG_NAME(SCL_FRM1_ADDR_CH3, "CIF_REG_SCL_FRM1_ADDR_CH3"),
491 [CIF_REG_SCL_VLW_CH3] = CIF_REG_NAME(SCL_VLW_CH3, "CIF_REG_SCL_VLW_CH3"),
492 [CIF_REG_SCL_BLC_CH0] = CIF_REG_NAME(SCL_BLC_CH0, "CIF_REG_SCL_BLC_CH0"),
493 [CIF_REG_SCL_BLC_CH1] = CIF_REG_NAME(SCL_BLC_CH1, "CIF_REG_SCL_BLC_CH1"),
494 [CIF_REG_SCL_BLC_CH2] = CIF_REG_NAME(SCL_BLC_CH2, "CIF_REG_SCL_BLC_CH2"),
495 [CIF_REG_SCL_BLC_CH3] = CIF_REG_NAME(SCL_BLC_CH3, "CIF_REG_SCL_BLC_CH3"),
496 [CIF_REG_TOISP0_CTRL] = CIF_REG_NAME(TOISP0_CH_CTRL, "CIF_REG_TOISP0_CTRL"),
497 [CIF_REG_TOISP0_SIZE] = CIF_REG_NAME(TOISP0_CROP_SIZE, "CIF_REG_TOISP0_SIZE"),
498 [CIF_REG_TOISP0_CROP] = CIF_REG_NAME(TOISP0_CROP, "CIF_REG_TOISP0_CROP"),
499 [CIF_REG_TOISP1_CTRL] = CIF_REG_NAME(TOISP1_CH_CTRL, "CIF_REG_TOISP1_CTRL"),
500 [CIF_REG_TOISP1_SIZE] = CIF_REG_NAME(TOISP1_CROP_SIZE, "CIF_REG_TOISP1_SIZE"),
501 [CIF_REG_TOISP1_CROP] = CIF_REG_NAME(TOISP1_CROP, "CIF_REG_TOISP1_CROP"),
502 [CIF_REG_GRF_CIFIO_CON] = CIF_REG_NAME(CIF_GRF_SOC_CON2, "CIF_REG_GRF_CIFIO_CON"),
503 };
504
505 static const struct vehicle_cif_reg rk3562_cif_regs[] = {
506 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID0_CTRL0,
507 "CIF_REG_MIPI_LVDS_ID0_CTRL0"),
508 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID0_CTRL1,
509 "CIF_REG_MIPI_LVDS_ID0_CTRL1"),
510 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID1_CTRL0,
511 "CIF_REG_MIPI_LVDS_ID1_CTRL0"),
512 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID1_CTRL1,
513 "CIF_REG_MIPI_LVDS_ID1_CTRL1"),
514 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID2_CTRL0,
515 "CIF_REG_MIPI_LVDS_ID2_CTRL0"),
516 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID2_CTRL1,
517 "CIF_REG_MIPI_LVDS_ID2_CTRL1"),
518 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG_NAME(CSI_MIPI0_ID3_CTRL0,
519 "CIF_REG_MIPI_LVDS_ID3_CTRL0"),
520 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG_NAME(CSI_MIPI0_ID3_CTRL1,
521 "CIF_REG_MIPI_LVDS_ID3_CTRL1"),
522 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG_NAME(CSI_MIPI0_CTRL, "CIF_REG_MIPI_LVDS_CTRL"),
523 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID0,
524 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0"),
525 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID0,
526 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0"),
527 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID0,
528 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0"),
529 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID0,
530 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0"),
531 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG_NAME(CSI_MIPI0_VLW_ID0,
532 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0"),
533 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID1,
534 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1"),
535 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID1,
536 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1"),
537 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID1,
538 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1"),
539 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID1,
540 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1"),
541 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG_NAME(CSI_MIPI0_VLW_ID1,
542 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1"),
543 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID2,
544 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2"),
545 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID2,
546 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2"),
547 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID2,
548 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2"),
549 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID2,
550 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2"),
551 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG_NAME(CSI_MIPI0_VLW_ID2,
552 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2"),
553 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_Y_ID3,
554 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3"),
555 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_Y_ID3,
556 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3"),
557 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM0_ADDR_UV_ID3,
558 "CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3"),
559 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG_NAME(CSI_MIPI0_FRM1_ADDR_UV_ID3,
560 "CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3"),
561 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG_NAME(CSI_MIPI0_VLW_ID3,
562 "CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3"),
563 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG_NAME(CSI_MIPI0_INTEN, "CIF_REG_MIPI_LVDS_INTEN"),
564 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG_NAME(CSI_MIPI0_INTSTAT, "CIF_REG_MIPI_LVDS_INTSTAT"),
565 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG_NAME(CSI_MIPI0_LINE_INT_NUM_ID0_1,
566 "CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1"),
567 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG_NAME(CSI_MIPI0_LINE_INT_NUM_ID2_3,
568 "CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3"),
569 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG_NAME(CSI_MIPI0_LINE_CNT_ID0_1,
570 "CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1"),
571 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG_NAME(CSI_MIPI0_LINE_CNT_ID2_3,
572 "CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3"),
573 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID0_CROP_START,
574 "CIF_REG_MIPI_LVDS_ID0_CROP_START"),
575 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID1_CROP_START,
576 "CIF_REG_MIPI_LVDS_ID1_CROP_START"),
577 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID2_CROP_START,
578 "CIF_REG_MIPI_LVDS_ID2_CROP_START"),
579 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG_NAME(CSI_MIPI0_ID3_CROP_START,
580 "CIF_REG_MIPI_LVDS_ID3_CROP_START"),
581 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC0,
582 "CIF_REG_MIPI_FRAME_NUM_VC0"),
583 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC1,
584 "CIF_REG_MIPI_FRAME_NUM_VC1"),
585 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC2,
586 "CIF_REG_MIPI_FRAME_NUM_VC2"),
587 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG_NAME(CSI_MIPI0_FRAME_NUM_VC3,
588 "CIF_REG_MIPI_FRAME_NUM_VC3"),
589 [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID0,
590 "CIF_REG_MIPI_EFFECT_CODE_ID0"),
591 [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID1,
592 "CIF_REG_MIPI_EFFECT_CODE_ID1"),
593 [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID2,
594 "CIF_REG_MIPI_EFFECT_CODE_ID2"),
595 [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG_NAME(CSI_MIPI0_EFFECT_CODE_ID3,
596 "CIF_REG_MIPI_EFFECT_CODE_ID3"),
597 [CIF_REG_MIPI_ON_PAD] = CIF_REG_NAME(CSI_MIPI0_ON_PAD, "CIF_REG_MIPI_ON_PAD"),
598 [CIF_REG_GLB_CTRL] = CIF_REG_NAME(GLB_CTRL, "CIF_REG_GLB_CTRL"),
599 [CIF_REG_GLB_INTEN] = CIF_REG_NAME(GLB_INTEN, "CIF_REG_GLB_INTEN"),
600 [CIF_REG_GLB_INTST] = CIF_REG_NAME(GLB_INTST, "CIF_REG_GLB_INTST"),
601 [CIF_REG_SCL_CH_CTRL] = CIF_REG_NAME(SCL_CH_CTRL, "CIF_REG_SCL_CH_CTRL"),
602 [CIF_REG_SCL_CTRL] = CIF_REG_NAME(SCL_CTRL, "CIF_REG_SCL_CTRL"),
603 [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG_NAME(SCL_FRM0_ADDR_CH0,
604 "CIF_REG_SCL_FRM0_ADDR_CH0"),
605 [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG_NAME(SCL_FRM1_ADDR_CH0,
606 "CIF_REG_SCL_FRM1_ADDR_CH0"),
607 [CIF_REG_SCL_VLW_CH0] = CIF_REG_NAME(SCL_VLW_CH0, "CIF_REG_SCL_VLW_CH0"),
608 [CIF_REG_SCL_BLC_CH0] = CIF_REG_NAME(SCL_BLC_CH0, "CIF_REG_SCL_BLC_CH0"),
609 [CIF_REG_TOISP0_CTRL] = CIF_REG_NAME(TOISP0_CH_CTRL, "CIF_REG_TOISP0_CTRL"),
610 [CIF_REG_TOISP0_SIZE] = CIF_REG_NAME(TOISP0_CROP_SIZE, "CIF_REG_TOISP0_SIZE"),
611 [CIF_REG_TOISP0_CROP] = CIF_REG_NAME(TOISP0_CROP, "CIF_REG_TOISP0_CROP"),
612 };
613
614 //define dphy and csi regs
615 static const struct grf_reg rk3568_grf_dphy_regs[] = {
616 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
617 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
618 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
619 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
620 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
621 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
622 [GRF_DPHY_ISP_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 12),
623 [GRF_DPHY_CIF_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 11),
624 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_VI_CON1, 1, 7),
625 };
626
627 static const struct csi2dphy_reg rk3568_csi2dphy_regs[] = {
628 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
629 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
630 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
631 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
632 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
633 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
634 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
635 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
636 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
637 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
638 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
639 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
640 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
641 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
642 };
643
644 static const struct grf_reg rk3588_grf_dphy_regs[] = {
645 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
646 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
647 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
648 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
649 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
650 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
651 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
652 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
653 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
654 [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
655 [GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
656 [GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
657 [GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
658 [GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
659 };
660
661 static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
662 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
663 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
664 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
665 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
666 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
667 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
668 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
669 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
670 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
671 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
672 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
673 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
674 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
675 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
676 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
677 };
678
679 static const struct grf_reg rk3588_grf_dcphy_regs[] = {
680 [GRF_CPHY_MODE] = GRF_REG(GRF_DCPHY_CON0, 9, 0),
681 };
682
683 static const struct csi2dphy_reg rk3588_csi2dcphy_regs[] = {
684 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_CLK_WR_THS_SETTLE),
685 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE0_WR_THS_SETTLE),
686 [CSI2PHY_LANE0_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC),
687 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE1_WR_THS_SETTLE),
688 [CSI2PHY_LANE1_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC),
689 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE2_WR_THS_SETTLE),
690 [CSI2PHY_LANE2_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC),
691 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE3_WR_THS_SETTLE),
692 [CSI2PHY_LANE3_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC),
693 [CSI2PHY_CLK_LANE_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_CLK_LANE_ENABLE),
694 [CSI2PHY_DATA_LANE0_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE0_ENABLE),
695 [CSI2PHY_DATA_LANE1_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE1_ENABLE),
696 [CSI2PHY_DATA_LANE2_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE2_ENABLE),
697 [CSI2PHY_DATA_LANE3_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE3_ENABLE),
698 [CSI2PHY_S0C_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0C_GNR_CON1),
699 [CSI2PHY_S0C_ANA_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0C_ANA_CON1),
700 [CSI2PHY_S0C_ANA_CON2] = CSI2PHY_REG(CSI2_DCPHY_S0C_ANA_CON2),
701 [CSI2PHY_S0C_ANA_CON3] = CSI2PHY_REG(CSI2_DCPHY_S0C_ANA_CON3),
702 [CSI2PHY_COMBO_S0D0_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_GNR_CON1),
703 [CSI2PHY_COMBO_S0D0_ANA_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_ANA_CON1),
704 [CSI2PHY_COMBO_S0D0_ANA_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_ANA_CON2),
705 [CSI2PHY_COMBO_S0D0_ANA_CON3] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_ANA_CON3),
706 [CSI2PHY_COMBO_S0D0_ANA_CON6] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_ANA_CON6),
707 [CSI2PHY_COMBO_S0D0_ANA_CON7] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_ANA_CON7),
708 [CSI2PHY_COMBO_S0D0_DESKEW_CON0] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_DESKEW_CON0),
709 [CSI2PHY_COMBO_S0D0_DESKEW_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_DESKEW_CON2),
710 [CSI2PHY_COMBO_S0D0_DESKEW_CON4] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_DESKEW_CON4),
711 [CSI2PHY_COMBO_S0D0_CRC_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_CRC_CON1),
712 [CSI2PHY_COMBO_S0D0_CRC_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_CRC_CON2),
713 [CSI2PHY_COMBO_S0D1_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_GNR_CON1),
714 [CSI2PHY_COMBO_S0D1_ANA_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_ANA_CON1),
715 [CSI2PHY_COMBO_S0D1_ANA_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_ANA_CON2),
716 [CSI2PHY_COMBO_S0D1_ANA_CON3] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_ANA_CON3),
717 [CSI2PHY_COMBO_S0D1_ANA_CON6] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_ANA_CON6),
718 [CSI2PHY_COMBO_S0D1_ANA_CON7] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_ANA_CON7),
719 [CSI2PHY_COMBO_S0D1_DESKEW_CON0] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_DESKEW_CON0),
720 [CSI2PHY_COMBO_S0D1_DESKEW_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_DESKEW_CON2),
721 [CSI2PHY_COMBO_S0D1_DESKEW_CON4] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_DESKEW_CON4),
722 [CSI2PHY_COMBO_S0D1_CRC_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_CRC_CON1),
723 [CSI2PHY_COMBO_S0D1_CRC_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_CRC_CON2),
724 [CSI2PHY_COMBO_S0D2_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_GNR_CON1),
725 [CSI2PHY_COMBO_S0D2_ANA_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_ANA_CON1),
726 [CSI2PHY_COMBO_S0D2_ANA_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_ANA_CON2),
727 [CSI2PHY_COMBO_S0D2_ANA_CON3] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_ANA_CON3),
728 [CSI2PHY_COMBO_S0D2_ANA_CON6] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_ANA_CON6),
729 [CSI2PHY_COMBO_S0D2_ANA_CON7] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_ANA_CON7),
730 [CSI2PHY_COMBO_S0D2_DESKEW_CON0] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_DESKEW_CON0),
731 [CSI2PHY_COMBO_S0D2_DESKEW_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_DESKEW_CON2),
732 [CSI2PHY_COMBO_S0D2_DESKEW_CON4] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_DESKEW_CON4),
733 [CSI2PHY_COMBO_S0D2_CRC_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_CRC_CON1),
734 [CSI2PHY_COMBO_S0D2_CRC_CON2] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_CRC_CON2),
735 [CSI2PHY_S0D3_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0D3_GNR_CON1),
736 [CSI2PHY_S0D3_ANA_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0D3_ANA_CON1),
737 [CSI2PHY_S0D3_ANA_CON2] = CSI2PHY_REG(CSI2_DCPHY_S0D3_ANA_CON2),
738 [CSI2PHY_S0D3_ANA_CON3] = CSI2PHY_REG(CSI2_DCPHY_S0D3_ANA_CON3),
739 [CSI2PHY_S0D3_DESKEW_CON0] = CSI2PHY_REG(CSI2_DCPHY_S0D3_DESKEW_CON0),
740 [CSI2PHY_S0D3_DESKEW_CON2] = CSI2PHY_REG(CSI2_DCPHY_S0D3_DESKEW_CON2),
741 [CSI2PHY_S0D3_DESKEW_CON4] = CSI2PHY_REG(CSI2_DCPHY_S0D3_DESKEW_CON4),
742 };
743
744 static const struct grf_reg rk3562_grf_dphy_regs[] = {
745 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON0, 4, 0),
746 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 4, 4),
747 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON0, 2, 4),
748 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON0, 2, 6),
749 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 8),
750 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 9),
751 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 10),
752 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 11),
753 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 12),
754 [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 13),
755 [GRF_DPHY1_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON1, 4, 0),
756 [GRF_DPHY1_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 4, 4),
757 [GRF_DPHY1_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON1, 2, 4),
758 [GRF_DPHY1_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON1, 2, 6),
759 [GRF_DPHY1_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 8),
760 [GRF_DPHY1_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 9),
761 [GRF_DPHY1_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 10),
762 [GRF_DPHY1_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 11),
763 };
764
765 static const struct csi2dphy_reg rk3562_csi2dphy_regs[] = {
766 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
767 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
768 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
769 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
770 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
771 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
772 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
773 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
774 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
775 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
776 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
777 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
778 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
779 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
780 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
781 };
782
783 //define dcphy params
784 static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
785 .vendor = PHY_VENDOR_SAMSUNG,
786 .lp_vol_ref = 3,
787 .lp_hys_sw = {3, 0, 0, 0},
788 .lp_escclk_pol_sel = {1, 0, 0, 0},
789 .skew_data_cal_clk = {0, 3, 3, 3},
790 .clk_hs_term_sel = 2,
791 .data_hs_term_sel = {2, 2, 2, 2},
792 .reserved = {0},
793 };
794
795 /* These tables must be sorted by .range_h ascending. */
796 static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = {
797 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
798 { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
799 { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
800 {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
801 {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
802 };
803
804 /* These tables must be sorted by .range_h ascending. */
805 static const struct hsfreq_range rk3588_csi2_dcphy_d_hw_hsfreq_ranges[] = {
806 { 80, 0x105}, { 100, 0x106}, { 120, 0x107}, { 140, 0x108},
807 { 160, 0x109}, { 180, 0x10a}, { 200, 0x10b}, { 220, 0x10c},
808 { 240, 0x10d}, { 270, 0x10e}, { 290, 0x10f}, { 310, 0x110},
809 { 330, 0x111}, { 350, 0x112}, { 370, 0x113}, { 390, 0x114},
810 { 410, 0x115}, { 430, 0x116}, { 450, 0x117}, { 470, 0x118},
811 { 490, 0x119}, { 510, 0x11a}, { 540, 0x11b}, { 560, 0x11c},
812 { 580, 0x11d}, { 600, 0x11e}, { 620, 0x11f}, { 640, 0x120},
813 { 660, 0x121}, { 680, 0x122}, { 700, 0x123}, { 720, 0x124},
814 { 740, 0x125}, { 760, 0x126}, { 790, 0x127}, { 810, 0x128},
815 { 830, 0x129}, { 850, 0x12a}, { 870, 0x12b}, { 890, 0x12c},
816 { 910, 0x12d}, { 930, 0x12e}, { 950, 0x12f}, { 970, 0x130},
817 { 990, 0x131}, {1010, 0x132}, {1030, 0x133}, {1060, 0x134},
818 {1080, 0x135}, {1100, 0x136}, {1120, 0x137}, {1140, 0x138},
819 {1160, 0x139}, {1180, 0x13a}, {1200, 0x13b}, {1220, 0x13c},
820 {1240, 0x13d}, {1260, 0x13e}, {1280, 0x13f}, {1310, 0x140},
821 {1330, 0x141}, {1350, 0x142}, {1370, 0x143}, {1390, 0x144},
822 {1410, 0x145}, {1430, 0x146}, {1450, 0x147}, {1470, 0x148},
823 {1490, 0x149}, {1580, 0x007}, {1740, 0x008}, {1910, 0x009},
824 {2070, 0x00a}, {2240, 0x00b}, {2410, 0x00c}, {2570, 0x00d},
825 {2740, 0x00e}, {2910, 0x00f}, {3070, 0x010}, {3240, 0x011},
826 {3410, 0x012}, {3570, 0x013}, {3740, 0x014}, {3890, 0x015},
827 {4070, 0x016}, {4240, 0x017}, {4400, 0x018}, {4500, 0x019},
828 };
829
830 static struct csi2_dphy_hw rk3568_csi2_dphy_hw = {
831 .dphy_clks = rk3568_csi2_dphy_hw_clks,
832 .num_dphy_clks = ARRAY_SIZE(rk3568_csi2_dphy_hw_clks),
833 .csi2_clks = rk3568_csi2_clks,
834 .num_csi2_clks = ARRAY_SIZE(rk3568_csi2_clks),
835 .csi2_rsts = rk3568_csi2_rsts,
836 .num_csi2_rsts = ARRAY_SIZE(rk3568_csi2_rsts),
837 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
838 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
839 .csi2dphy_regs = rk3568_csi2dphy_regs,
840 .grf_regs = rk3568_grf_dphy_regs,
841 .chip_id = CHIP_ID_RK3568,
842 };
843
844 static struct csi2_dphy_hw rk3588_csi2_dphy_hw = {
845 .dphy_clks = rk3588_csi2_dphy_hw_clks,
846 .num_dphy_clks = ARRAY_SIZE(rk3588_csi2_dphy_hw_clks),
847 .dphy_rsts = rk3588_csi2_dphy_hw_rsts,
848 .num_dphy_rsts = ARRAY_SIZE(rk3588_csi2_dphy_hw_rsts),
849 .csi2_clks = rk3588_csi2_clks,
850 .num_csi2_clks = ARRAY_SIZE(rk3588_csi2_clks),
851 .csi2_rsts = rk3588_csi2_rsts,
852 .num_csi2_rsts = ARRAY_SIZE(rk3588_csi2_rsts),
853 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
854 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
855 .csi2dphy_regs = rk3588_csi2dphy_regs,
856 .grf_regs = rk3588_grf_dphy_regs,
857 .chip_id = CHIP_ID_RK3588,
858 };
859
860 static struct csi2_dphy_hw rk3588_csi2_dcphy_hw = {
861 .dphy_clks = rk3588_csi2_dphy_hw_clks,
862 .num_dphy_clks = ARRAY_SIZE(rk3588_csi2_dphy_hw_clks),
863 .csi2_clks = rk3588_csi2_dcphy_clks,
864 .num_csi2_clks = ARRAY_SIZE(rk3588_csi2_dcphy_clks),
865 .csi2_rsts = rk3588_csi2_rsts,
866 .num_csi2_rsts = ARRAY_SIZE(rk3588_csi2_rsts),
867 .hsfreq_ranges = rk3588_csi2_dcphy_d_hw_hsfreq_ranges,
868 .num_hsfreq_ranges = ARRAY_SIZE(rk3588_csi2_dcphy_d_hw_hsfreq_ranges),
869 .csi2dphy_regs = rk3588_csi2dcphy_regs,
870 .grf_regs = rk3588_grf_dcphy_regs,
871 .chip_id = CHIP_ID_RK3588_DCPHY,
872 };
873
874 static struct csi2_dphy_hw rk3562_csi2_dphy_hw = {
875 .dphy_clks = rk3562_csi2_dphy_hw_clks,
876 .num_dphy_clks = ARRAY_SIZE(rk3562_csi2_dphy_hw_clks),
877 .dphy_rsts = rk3562_csi2_dphy_hw_rsts,
878 .num_dphy_rsts = ARRAY_SIZE(rk3562_csi2_dphy_hw_rsts),
879 .csi2_clks = rk3562_csi2_clks,
880 .num_csi2_clks = ARRAY_SIZE(rk3562_csi2_clks),
881 .csi2_rsts = rk3562_csi2_rsts,
882 .num_csi2_rsts = ARRAY_SIZE(rk3562_csi2_rsts),
883 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
884 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
885 .csi2dphy_regs = rk3562_csi2dphy_regs,
886 .grf_regs = rk3562_grf_dphy_regs,
887 .chip_id = CHIP_ID_RK3562,
888 };
889
890 static const struct cif_input_fmt in_fmts[] = {
891 {
892 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
893 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YUYV,
894 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
895 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YUYV,
896 .fmt_type = CIF_FMT_TYPE_YUV,
897 .field = V4L2_FIELD_NONE,
898 }, {
899 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
900 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YUYV,
901 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
902 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YUYV,
903 .fmt_type = CIF_FMT_TYPE_YUV,
904 .field = V4L2_FIELD_INTERLACED,
905 }, {
906 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
907 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YVYU,
908 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
909 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YVYU,
910 .fmt_type = CIF_FMT_TYPE_YUV,
911 .field = V4L2_FIELD_NONE,
912 }, {
913 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
914 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YVYU,
915 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
916 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YVYU,
917 .fmt_type = CIF_FMT_TYPE_YUV,
918 .field = V4L2_FIELD_INTERLACED,
919 }, {
920 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
921 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_UYVY,
922 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
923 .csi_yuv_order = CSI_YUV_INPUT_ORDER_UYVY,
924 .fmt_type = CIF_FMT_TYPE_YUV,
925 .field = V4L2_FIELD_NONE,
926 }, {
927 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
928 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_UYVY,
929 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
930 .csi_yuv_order = CSI_YUV_INPUT_ORDER_UYVY,
931 .fmt_type = CIF_FMT_TYPE_YUV,
932 .field = V4L2_FIELD_INTERLACED,
933 }, {
934 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
935 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_VYUY,
936 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
937 .csi_yuv_order = CSI_YUV_INPUT_ORDER_VYUY,
938 .fmt_type = CIF_FMT_TYPE_YUV,
939 .field = V4L2_FIELD_NONE,
940 }, {
941 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
942 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_VYUY,
943 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
944 .csi_yuv_order = CSI_YUV_INPUT_ORDER_VYUY,
945 .fmt_type = CIF_FMT_TYPE_YUV,
946 .field = V4L2_FIELD_INTERLACED,
947 }, {
948 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
949 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
950 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
951 .fmt_type = CIF_FMT_TYPE_RAW,
952 .field = V4L2_FIELD_NONE,
953 }, {
954 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
955 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
956 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
957 .fmt_type = CIF_FMT_TYPE_RAW,
958 .field = V4L2_FIELD_NONE,
959 }, {
960 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
961 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
962 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
963 .fmt_type = CIF_FMT_TYPE_RAW,
964 .field = V4L2_FIELD_NONE,
965 }, {
966 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
967 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
968 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
969 .fmt_type = CIF_FMT_TYPE_RAW,
970 .field = V4L2_FIELD_NONE,
971 }, {
972 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
973 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
974 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
975 .fmt_type = CIF_FMT_TYPE_RAW,
976 .field = V4L2_FIELD_NONE,
977 }, {
978 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
979 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
980 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
981 .fmt_type = CIF_FMT_TYPE_RAW,
982 .field = V4L2_FIELD_NONE,
983 }, {
984 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
985 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
986 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
987 .fmt_type = CIF_FMT_TYPE_RAW,
988 .field = V4L2_FIELD_NONE,
989 }, {
990 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
991 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
992 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
993 .fmt_type = CIF_FMT_TYPE_RAW,
994 .field = V4L2_FIELD_NONE,
995 }, {
996 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
997 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
998 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
999 .fmt_type = CIF_FMT_TYPE_RAW,
1000 .field = V4L2_FIELD_NONE,
1001 }, {
1002 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
1003 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
1004 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1005 .fmt_type = CIF_FMT_TYPE_RAW,
1006 .field = V4L2_FIELD_NONE,
1007 }, {
1008 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
1009 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
1010 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1011 .fmt_type = CIF_FMT_TYPE_RAW,
1012 .field = V4L2_FIELD_NONE,
1013 }, {
1014 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
1015 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
1016 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1017 .fmt_type = CIF_FMT_TYPE_RAW,
1018 .field = V4L2_FIELD_NONE,
1019 }, {
1020 .mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
1021 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
1022 .field = V4L2_FIELD_NONE,
1023 }, {
1024 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
1025 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
1026 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1027 .fmt_type = CIF_FMT_TYPE_RAW,
1028 .field = V4L2_FIELD_NONE,
1029 }, {
1030 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
1031 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
1032 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
1033 .fmt_type = CIF_FMT_TYPE_RAW,
1034 .field = V4L2_FIELD_NONE,
1035 }, {
1036 .mbus_code = MEDIA_BUS_FMT_Y12_1X12,
1037 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
1038 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1039 .fmt_type = CIF_FMT_TYPE_RAW,
1040 .field = V4L2_FIELD_NONE,
1041 }
1042 };
1043
1044 static const struct cif_output_fmt out_fmts[] = {
1045 {
1046 .fourcc = V4L2_PIX_FMT_NV16,
1047 .cplanes = 2,
1048 .mplanes = 1,
1049 .fmt_val = YUV_OUTPUT_422 | UV_STORAGE_ORDER_UVUV,
1050 .bpp = { 8, 16 },
1051 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
1052 .fmt_type = CIF_FMT_TYPE_YUV,
1053 }, {
1054 .fourcc = V4L2_PIX_FMT_NV61,
1055 .fmt_val = YUV_OUTPUT_422 | UV_STORAGE_ORDER_VUVU,
1056 .cplanes = 2,
1057 .mplanes = 1,
1058 .bpp = { 8, 16 },
1059 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
1060 .fmt_type = CIF_FMT_TYPE_YUV,
1061 }, {
1062 .fourcc = V4L2_PIX_FMT_NV12,
1063 .fmt_val = YUV_OUTPUT_420 | UV_STORAGE_ORDER_UVUV,
1064 .cplanes = 2,
1065 .mplanes = 1,
1066 .bpp = { 8, 16 },
1067 .csi_fmt_val = CSI_WRDDR_TYPE_YUV420SP,
1068 .fmt_type = CIF_FMT_TYPE_YUV,
1069 }, {
1070 .fourcc = V4L2_PIX_FMT_NV21,
1071 .fmt_val = YUV_OUTPUT_420 | UV_STORAGE_ORDER_VUVU,
1072 .cplanes = 2,
1073 .mplanes = 1,
1074 .bpp = { 8, 16 },
1075 .csi_fmt_val = CSI_WRDDR_TYPE_YUV420SP,
1076 .fmt_type = CIF_FMT_TYPE_YUV,
1077 }, {
1078 .fourcc = V4L2_PIX_FMT_YUYV,
1079 .cplanes = 2,
1080 .mplanes = 1,
1081 .bpp = { 8, 16 },
1082 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1083 .fmt_type = CIF_FMT_TYPE_YUV,
1084 }, {
1085 .fourcc = V4L2_PIX_FMT_YVYU,
1086 .cplanes = 2,
1087 .mplanes = 1,
1088 .bpp = { 8, 16 },
1089 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1090 .fmt_type = CIF_FMT_TYPE_YUV,
1091 }, {
1092 .fourcc = V4L2_PIX_FMT_UYVY,
1093 .cplanes = 2,
1094 .mplanes = 1,
1095 .bpp = { 8, 16 },
1096 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1097 .fmt_type = CIF_FMT_TYPE_YUV,
1098 }, {
1099 .fourcc = V4L2_PIX_FMT_VYUY,
1100 .cplanes = 2,
1101 .mplanes = 1,
1102 .bpp = { 8, 16 },
1103 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1104 .fmt_type = CIF_FMT_TYPE_YUV,
1105 }, {
1106 .fourcc = V4L2_PIX_FMT_RGB24,
1107 .cplanes = 1,
1108 .mplanes = 1,
1109 .bpp = { 24 },
1110 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
1111 .fmt_type = CIF_FMT_TYPE_RAW,
1112 }, {
1113 .fourcc = V4L2_PIX_FMT_RGB565,
1114 .cplanes = 1,
1115 .mplanes = 1,
1116 .bpp = { 16 },
1117 .fmt_type = CIF_FMT_TYPE_RAW,
1118 }, {
1119 .fourcc = V4L2_PIX_FMT_BGR666,
1120 .cplanes = 1,
1121 .mplanes = 1,
1122 .bpp = { 18 },
1123 .fmt_type = CIF_FMT_TYPE_RAW,
1124 }, {
1125 .fourcc = V4L2_PIX_FMT_SRGGB8,
1126 .cplanes = 1,
1127 .mplanes = 1,
1128 .bpp = { 8 },
1129 .raw_bpp = 8,
1130 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1131 .fmt_type = CIF_FMT_TYPE_RAW,
1132 }, {
1133 .fourcc = V4L2_PIX_FMT_SGRBG8,
1134 .cplanes = 1,
1135 .mplanes = 1,
1136 .bpp = { 8 },
1137 .raw_bpp = 8,
1138 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1139 .fmt_type = CIF_FMT_TYPE_RAW,
1140 }, {
1141 .fourcc = V4L2_PIX_FMT_SGBRG8,
1142 .cplanes = 1,
1143 .mplanes = 1,
1144 .bpp = { 8 },
1145 .raw_bpp = 8,
1146 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1147 .fmt_type = CIF_FMT_TYPE_RAW,
1148 }, {
1149 .fourcc = V4L2_PIX_FMT_SBGGR8,
1150 .cplanes = 1,
1151 .mplanes = 1,
1152 .bpp = { 8 },
1153 .raw_bpp = 8,
1154 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
1155 .fmt_type = CIF_FMT_TYPE_RAW,
1156 }, {
1157 .fourcc = V4L2_PIX_FMT_SRGGB10,
1158 .cplanes = 1,
1159 .mplanes = 1,
1160 .bpp = { 16 },
1161 .raw_bpp = 10,
1162 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
1163 .fmt_type = CIF_FMT_TYPE_RAW,
1164 }, {
1165 .fourcc = V4L2_PIX_FMT_SGRBG10,
1166 .cplanes = 1,
1167 .mplanes = 1,
1168 .bpp = { 16 },
1169 .raw_bpp = 10,
1170 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
1171 .fmt_type = CIF_FMT_TYPE_RAW,
1172 }, {
1173 .fourcc = V4L2_PIX_FMT_SGBRG10,
1174 .cplanes = 1,
1175 .mplanes = 1,
1176 .bpp = { 16 },
1177 .raw_bpp = 10,
1178 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
1179 .fmt_type = CIF_FMT_TYPE_RAW,
1180 }, {
1181 .fourcc = V4L2_PIX_FMT_SBGGR10,
1182 .cplanes = 1,
1183 .mplanes = 1,
1184 .bpp = { 16 },
1185 .raw_bpp = 10,
1186 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
1187 .fmt_type = CIF_FMT_TYPE_RAW,
1188 }, {
1189 .fourcc = V4L2_PIX_FMT_SRGGB12,
1190 .cplanes = 1,
1191 .mplanes = 1,
1192 .bpp = { 16 },
1193 .raw_bpp = 12,
1194 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1195 .fmt_type = CIF_FMT_TYPE_RAW,
1196 }, {
1197 .fourcc = V4L2_PIX_FMT_SGRBG12,
1198 .cplanes = 1,
1199 .mplanes = 1,
1200 .bpp = { 16 },
1201 .raw_bpp = 12,
1202 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1203 .fmt_type = CIF_FMT_TYPE_RAW,
1204 }, {
1205 .fourcc = V4L2_PIX_FMT_SGBRG12,
1206 .cplanes = 1,
1207 .mplanes = 1,
1208 .bpp = { 16 },
1209 .raw_bpp = 12,
1210 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1211 .fmt_type = CIF_FMT_TYPE_RAW,
1212 }, {
1213 .fourcc = V4L2_PIX_FMT_SBGGR12,
1214 .cplanes = 1,
1215 .mplanes = 1,
1216 .bpp = { 16 },
1217 .raw_bpp = 12,
1218 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
1219 .fmt_type = CIF_FMT_TYPE_RAW,
1220 }, {
1221 .fourcc = V4L2_PIX_FMT_SBGGR16,
1222 .cplanes = 1,
1223 .mplanes = 1,
1224 .bpp = { 16 },
1225 .raw_bpp = 16,
1226 .fmt_type = CIF_FMT_TYPE_RAW,
1227 }, {
1228 .fourcc = V4L2_PIX_FMT_Y16,
1229 .cplanes = 1,
1230 .mplanes = 1,
1231 .bpp = { 16 },
1232 .fmt_type = CIF_FMT_TYPE_RAW,
1233 }
1234
1235 /* TODO: We can support NV12M/NV21M/NV16M/NV61M too */
1236 };
1237
rkcif_write_reg(struct vehicle_cif * cif,enum cif_reg_index index,u32 val)1238 static void rkcif_write_reg(struct vehicle_cif *cif,
1239 enum cif_reg_index index, u32 val)
1240 {
1241 void __iomem *base = cif->base;
1242 const struct vehicle_cif_reg *reg = &cif->cif_regs[index];
1243 int csi_offset = 0;
1244
1245 if (cif->inf_id == RKCIF_MIPI_LVDS &&
1246 index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
1247 index <= CIF_REG_MIPI_ON_PAD) {
1248 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
1249 csi_offset = cif->csi_host_idx * 0x100;
1250 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
1251 if (cif->csi_host_idx < 3)
1252 csi_offset = cif->csi_host_idx * 0x200;
1253 else
1254 csi_offset = 0x500;
1255 }
1256 }
1257
1258 if (index < CIF_REG_INDEX_MAX) {
1259 if (index == CIF_REG_DVP_CTRL ||
1260 ((index != CIF_REG_DVP_CTRL) && (reg->offset != 0x0))) {
1261 write_reg(base, reg->offset + csi_offset, val);
1262 } else {
1263 VEHICLE_INFO("write index(%d) reg[%s]: 0x%x failed, maybe useless!!!\n",
1264 index, reg->name, val);
1265 }
1266 }
1267 VEHICLE_DG("@%s register[%s] offset(0x%x) csi_offset(0x%x) value:0x%x !\n",
1268 __func__, reg->name, reg->offset, csi_offset, val);
1269 }
1270
rkcif_write_reg_or(struct vehicle_cif * cif,enum cif_reg_index index,u32 val)1271 static void rkcif_write_reg_or(struct vehicle_cif *cif,
1272 enum cif_reg_index index, u32 val)
1273 {
1274 void __iomem *base = cif->base;
1275 const struct vehicle_cif_reg *reg = &cif->cif_regs[index];
1276 unsigned int reg_val = 0x0;
1277 int csi_offset = 0;
1278
1279 if (cif->inf_id == RKCIF_MIPI_LVDS &&
1280 index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
1281 index <= CIF_REG_MIPI_ON_PAD) {
1282 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
1283 csi_offset = cif->csi_host_idx * 0x100;
1284 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
1285 if (cif->csi_host_idx < 3)
1286 csi_offset = cif->csi_host_idx * 0x200;
1287 else
1288 csi_offset = 0x500;
1289 }
1290 }
1291
1292 if (index < CIF_REG_INDEX_MAX) {
1293 if (index == CIF_REG_DVP_CTRL ||
1294 ((index != CIF_REG_DVP_CTRL) && (reg->offset != 0x0))) {
1295 reg_val = read_reg(base, reg->offset + csi_offset);
1296 reg_val |= val;
1297 write_reg(base, reg->offset + csi_offset, reg_val);
1298 } else {
1299 VEHICLE_INFO("write index(%d) reg[%s]: 0x%x failed, maybe useless!!!\n",
1300 index, reg->name, val);
1301 }
1302 }
1303 VEHICLE_DG("@%s register[%s] offset(0x%x) csi_offset(0x%x) value:0x%x !\n",
1304 __func__, reg->name, reg->offset, csi_offset, reg_val);
1305 }
1306
rkcif_write_reg_and(struct vehicle_cif * cif,enum cif_reg_index index,u32 val)1307 static void rkcif_write_reg_and(struct vehicle_cif *cif,
1308 enum cif_reg_index index, u32 val)
1309 {
1310 void __iomem *base = cif->base;
1311 const struct vehicle_cif_reg *reg = &cif->cif_regs[index];
1312 unsigned int reg_val = 0x0;
1313 int csi_offset = 0;
1314
1315 if (cif->inf_id == RKCIF_MIPI_LVDS &&
1316 index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
1317 index <= CIF_REG_MIPI_ON_PAD) {
1318 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
1319 csi_offset = cif->csi_host_idx * 0x100;
1320 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
1321 if (cif->csi_host_idx < 3)
1322 csi_offset = cif->csi_host_idx * 0x200;
1323 else
1324 csi_offset = 0x500;
1325 }
1326 }
1327
1328 if (index < CIF_REG_INDEX_MAX) {
1329 if (index == CIF_REG_DVP_CTRL ||
1330 ((index != CIF_REG_DVP_CTRL) && (reg->offset != 0x0))) {
1331 reg_val = read_reg(base, reg->offset + csi_offset);
1332 reg_val &= val;
1333 write_reg(base, reg->offset + csi_offset, reg_val);
1334 } else {
1335 VEHICLE_INFO("write index(%d) reg[%s]: 0x%x failed, maybe useless!!!\n",
1336 index, reg->name, val);
1337 }
1338 }
1339 VEHICLE_DG("@%s register[%s] offset(0x%x) csi_offset(0x%x) value:0x%x !\n",
1340 __func__, reg->name, reg->offset, csi_offset, reg_val);
1341 }
1342
rkcif_read_reg(struct vehicle_cif * cif,enum cif_reg_index index)1343 static unsigned int rkcif_read_reg(struct vehicle_cif *cif,
1344 enum cif_reg_index index)
1345 {
1346 unsigned int val = 0x0;
1347 void __iomem *base = cif->base;
1348 const struct vehicle_cif_reg *reg = &cif->cif_regs[index];
1349 int csi_offset = 0;
1350
1351 if (cif->inf_id == RKCIF_MIPI_LVDS &&
1352 index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
1353 index <= CIF_REG_MIPI_ON_PAD) {
1354 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
1355 csi_offset = cif->csi_host_idx * 0x100;
1356 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
1357 if (cif->csi_host_idx < 3)
1358 csi_offset = cif->csi_host_idx * 0x200;
1359 else
1360 csi_offset = 0x500;
1361 }
1362 }
1363
1364 if (index < CIF_REG_INDEX_MAX) {
1365 if (index == CIF_REG_DVP_CTRL ||
1366 ((index != CIF_REG_DVP_CTRL) && (reg->offset != 0x0)))
1367 val = read_reg(base, reg->offset + csi_offset);
1368 else
1369 VEHICLE_INFO("read index(%d) reg[%s]: 0x%x failed, maybe useless!!!\n",
1370 index, reg->name, val);
1371 }
1372 VEHICLE_DG("@%s register[%s] offset(0x%x) csi_offset(0x%x) value:0x%x !\n",
1373 __func__, reg->name, reg->offset, csi_offset, val);
1374 return val;
1375 }
1376
rkvehicle_cif_write_grf_reg(struct vehicle_cif * cif,enum cif_reg_index index,u32 val)1377 static void rkvehicle_cif_write_grf_reg(struct vehicle_cif *cif,
1378 enum cif_reg_index index, u32 val)
1379 {
1380 const struct vehicle_cif_reg *reg = &cif->cif_regs[index];
1381
1382 if (index < CIF_REG_INDEX_MAX) {
1383 if (index > CIF_REG_DVP_CTRL) {
1384 if (!IS_ERR(cif->regmap_grf))
1385 regmap_write(cif->regmap_grf, reg->offset, val);
1386 } else {
1387 VEHICLE_INFO("write index(%d) reg[%s]: 0x%x failed, maybe useless!!!\n",
1388 index, reg->name, val);
1389 }
1390 VEHICLE_DG("@%s reg[%s] offset(0x%x): 0x%x !\n",
1391 __func__, reg->name, reg->offset, val);
1392 }
1393 }
1394
rkvehicle_cif_read_grf_reg(struct vehicle_cif * cif,enum cif_reg_index index)1395 static u32 rkvehicle_cif_read_grf_reg(struct vehicle_cif *cif,
1396 enum cif_reg_index index)
1397 {
1398 const struct vehicle_cif_reg *reg = &cif->cif_regs[index];
1399 u32 val = 0xffff;
1400
1401 if (index < CIF_REG_INDEX_MAX) {
1402 if (index > CIF_REG_DVP_CTRL) {
1403 if (!IS_ERR(cif->regmap_grf))
1404 regmap_read(cif->regmap_grf, reg->offset, &val);
1405 } else {
1406 VEHICLE_INFO("read index(%d) reg[%s]: 0x%x failed, maybe useless!!!\n",
1407 index, reg->name, val);
1408 }
1409 VEHICLE_DG("@%s reg[%s] offset(0x%x): 0x%x !\n",
1410 __func__, reg->name, reg->offset, val);
1411 }
1412
1413 return val;
1414 }
1415
write_csi2_dphy_reg(struct csi2_dphy_hw * hw,int index,u32 value)1416 static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw,
1417 int index, u32 value)
1418 {
1419 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
1420
1421 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
1422 (index == CSI2PHY_CLK_LANE_ENABLE) ||
1423 ((index != CSI2PHY_REG_CTRL_LANE_ENABLE) &&
1424 (reg->offset != 0x0)))
1425 writel(value, hw->csi2_dphy_base + reg->offset);
1426
1427 VEHICLE_DG("@%s offset(0x%x) reg val: 0x%x !\n",
1428 __func__, reg->offset, value);
1429 }
1430
write_csi2_dphy_reg_mask(struct csi2_dphy_hw * hw,int index,u32 value,u32 mask)1431 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw,
1432 int index, u32 value, u32 mask)
1433 {
1434 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
1435 u32 read_val = 0;
1436
1437 read_val = readl(hw->csi2_dphy_base + reg->offset);
1438 read_val &= ~mask;
1439 read_val |= value;
1440 writel(read_val, hw->csi2_dphy_base + reg->offset);
1441 }
1442
read_csi2_dphy_reg(struct csi2_dphy_hw * hw,int index,u32 * value)1443 static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
1444 int index, u32 *value)
1445 {
1446 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
1447
1448 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
1449 (index == CSI2PHY_CLK_LANE_ENABLE) ||
1450 ((index != CSI2PHY_REG_CTRL_LANE_ENABLE) &&
1451 (reg->offset != 0x0)))
1452 *value = readl(hw->csi2_dphy_base + reg->offset);
1453
1454 VEHICLE_DG("@%s offset(0x%x) reg val: 0x%x !\n",
1455 __func__, reg->offset, *value);
1456 }
1457
csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw * hw,int hsfreq,enum csi2_dphy_lane lane)1458 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw,
1459 int hsfreq,
1460 enum csi2_dphy_lane lane)
1461 {
1462 unsigned int val = 0;
1463 unsigned int offset;
1464
1465 switch (lane) {
1466 case CSI2_DPHY_LANE_CLOCK:
1467 offset = CSI2PHY_CLK_THS_SETTLE;
1468 break;
1469 case CSI2_DPHY_LANE_CLOCK1:
1470 offset = CSI2PHY_CLK1_THS_SETTLE;
1471 break;
1472 case CSI2_DPHY_LANE_DATA0:
1473 offset = CSI2PHY_LANE0_THS_SETTLE;
1474 break;
1475 case CSI2_DPHY_LANE_DATA1:
1476 offset = CSI2PHY_LANE1_THS_SETTLE;
1477 break;
1478 case CSI2_DPHY_LANE_DATA2:
1479 offset = CSI2PHY_LANE2_THS_SETTLE;
1480 break;
1481 case CSI2_DPHY_LANE_DATA3:
1482 offset = CSI2PHY_LANE3_THS_SETTLE;
1483 break;
1484 default:
1485 return;
1486 }
1487
1488 read_csi2_dphy_reg(hw, offset, &val);
1489 val = (val & ~0x7f) | hsfreq;
1490 write_csi2_dphy_reg(hw, offset, val);
1491 }
1492
rkvehicle_cif_cfg_dvp_clk_sampling_edge(struct vehicle_cif * cif,enum rkcif_clk_edge edge)1493 static void rkvehicle_cif_cfg_dvp_clk_sampling_edge(struct vehicle_cif *cif,
1494 enum rkcif_clk_edge edge)
1495 {
1496 u32 val = 0x0;
1497
1498 if (!IS_ERR(cif->regmap_grf)) {
1499 if (cif->chip_id == CHIP_RK3568_VEHICLE_CIF) {
1500 if (edge == RKCIF_CLK_RISING)
1501 val = RK3568_CIF_PCLK_SAMPLING_EDGE_RISING;
1502 else
1503 val = RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING;
1504 }
1505 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
1506 if (edge == RKCIF_CLK_RISING)
1507 val = RK3588_CIF_PCLK_SAMPLING_EDGE_RISING;
1508 else
1509 val = RK3588_CIF_PCLK_SAMPLING_EDGE_FALLING;
1510 }
1511 rkvehicle_cif_write_grf_reg(cif, CIF_REG_GRF_CIFIO_CON, val);
1512 }
1513 }
1514
rkcif_dvp_get_input_yuv_order(struct vehicle_cfg * cfg)1515 static int rkcif_dvp_get_input_yuv_order(struct vehicle_cfg *cfg)
1516 {
1517 unsigned int mask;
1518
1519 switch (cfg->mbus_code) {
1520 case MEDIA_BUS_FMT_UYVY8_2X8:
1521 mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
1522 break;
1523 case MEDIA_BUS_FMT_VYUY8_2X8:
1524 mask = CSI_YUV_INPUT_ORDER_VYUY >> 11;
1525 break;
1526 case MEDIA_BUS_FMT_YUYV8_2X8:
1527 mask = CSI_YUV_INPUT_ORDER_YUYV >> 11;
1528 break;
1529 case MEDIA_BUS_FMT_YVYU8_2X8:
1530 mask = CSI_YUV_INPUT_ORDER_YVYU >> 11;
1531 break;
1532 default:
1533 mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
1534 break;
1535 }
1536 return mask;
1537 }
1538
cif_stream_setup(struct vehicle_cif * cif)1539 static int cif_stream_setup(struct vehicle_cif *cif)
1540 {
1541 struct vehicle_cfg *cfg = &cif->cif_cfg;
1542 u32 val, mbus_flags,
1543 xfer_mode = 0, yc_swap = 0,
1544 inputmode = 0, mipimode = 0,
1545 input_format = 0, output_format = 0, crop = 0,
1546 out_fmt_mask = 0,
1547 multi_id_en = BT656_1120_MULTI_ID_DISABLE,
1548 multi_id_mode = BT656_1120_MULTI_ID_MODE_1,
1549 multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB,
1550 bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES;
1551 u32 sav_detect = BT656_DETECT_SAV;
1552 u32 in_fmt_yuv_order = 0;
1553
1554 mbus_flags = cfg->mbus_flags;
1555 /* set dvp clk sample edge */
1556 if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1557 rkvehicle_cif_cfg_dvp_clk_sampling_edge(cif, RKCIF_CLK_RISING);
1558 else
1559 rkvehicle_cif_cfg_dvp_clk_sampling_edge(cif, RKCIF_CLK_FALLING);
1560
1561 inputmode = cfg->input_format<<2; //INPUT_MODE_YUV or INPUT_MODE_BT656_YUV422
1562 //YUV_INPUT_ORDER_UYVY, MEDIA_BUS_FMT_UYVY8_2X8, CCIR_INPUT_ORDER_ODD
1563 input_format = (cfg->yuv_order<<5) | YUV_INPUT_422 | (cfg->field_order<<9);
1564 if (cfg->output_format == CIF_OUTPUT_FORMAT_420)
1565 output_format = YUV_OUTPUT_420 | UV_STORAGE_ORDER_UVUV;
1566 else
1567 output_format = YUV_OUTPUT_422 | UV_STORAGE_ORDER_UVUV;
1568
1569 if (cif->chip_id == CHIP_RK3568_VEHICLE_CIF) {
1570 val = cfg->vsync | (cfg->href<<1) | inputmode | mipimode
1571 | input_format | output_format
1572 | xfer_mode | yc_swap | multi_id_en
1573 | multi_id_sel | multi_id_mode | bt1120_edge_mode;
1574 } else {
1575 out_fmt_mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) |
1576 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
1577 in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order(cfg);
1578 val = cfg->vsync | (cfg->href<<1) | inputmode
1579 | in_fmt_yuv_order | out_fmt_mask
1580 | yc_swap | multi_id_en | multi_id_sel
1581 | sav_detect | multi_id_mode | bt1120_edge_mode;
1582 }
1583
1584 rkcif_write_reg(cif, CIF_REG_DVP_FOR, val);
1585
1586 rkcif_write_reg(cif, CIF_REG_DVP_VIR_LINE_WIDTH, cfg->width);
1587 rkcif_write_reg(cif, CIF_REG_DVP_SET_SIZE,
1588 cfg->width | (cfg->height << 16));
1589
1590 crop = (cfg->start_x | (cfg->start_y<<16));
1591 rkcif_write_reg(cif, CIF_REG_DVP_CROP, crop);
1592
1593 rkcif_write_reg(cif, CIF_REG_DVP_FRAME_STATUS, FRAME_STAT_CLS);
1594
1595 if (cif->chip_id < CHIP_RK3588_VEHICLE_CIF) {
1596 rkcif_write_reg(cif, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
1597 rkcif_write_reg(cif, CIF_REG_DVP_SCL_CTRL, ENABLE_YUV_16BIT_BYPASS);
1598 rkcif_write_reg(cif, CIF_REG_DVP_INTEN,
1599 FRAME_END_EN | INTSTAT_ERR |
1600 PST_INF_FRAME_END);
1601 /* enable line int for sof */
1602 rkcif_write_reg(cif, CIF_REG_DVP_LINE_INT_NUM, 0x1);
1603 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, LINE_INT_EN);
1604 } else {
1605 rkcif_write_reg(cif, CIF_REG_DVP_INTSTAT, 0x3c3ffff);
1606 rkcif_write_reg_or(cif, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
1607 }
1608
1609 cif->interlaced_enable = false;
1610
1611 return 0;
1612 }
1613
csi2_dphy_write_sys_grf_reg(struct csi2_dphy_hw * hw,int index,u8 value)1614 static inline void csi2_dphy_write_sys_grf_reg(struct csi2_dphy_hw *hw,
1615 int index, u8 value)
1616 {
1617 const struct grf_reg *reg = &hw->grf_regs[index];
1618 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
1619
1620 if (reg->shift)
1621 regmap_write(hw->regmap_sys_grf, reg->offset, val);
1622 }
1623
csi2_dphy_write_grf_reg(struct csi2_dphy_hw * hw,int index,u8 value)1624 static inline void csi2_dphy_write_grf_reg(struct csi2_dphy_hw *hw,
1625 int index, u8 value)
1626 {
1627 const struct grf_reg *reg = &hw->grf_regs[index];
1628 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
1629
1630 if (reg->shift)
1631 regmap_write(hw->regmap_grf, reg->offset, val);
1632 }
1633
csi2_dphy_read_grf_reg(struct csi2_dphy_hw * hw,int index)1634 static inline u32 csi2_dphy_read_grf_reg(struct csi2_dphy_hw *hw, int index)
1635 {
1636 const struct grf_reg *reg = &hw->grf_regs[index];
1637 unsigned int val = 0;
1638
1639 if (reg->shift) {
1640 regmap_read(hw->regmap_grf, reg->offset, &val);
1641 val = (val >> reg->shift) & reg->mask;
1642 }
1643
1644 return val;
1645 }
1646
csi2_dphy_config_dual_mode(struct vehicle_cif * cif)1647 static void csi2_dphy_config_dual_mode(struct vehicle_cif *cif)
1648 {
1649 struct csi2_dphy_hw *hw = cif->dphy_hw;
1650 u32 val;
1651
1652 val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
1653 if (cif->dphy_hw->phy_index < 3) {
1654 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
1655 GENMASK(cif->cif_cfg.lanes - 1, 0));
1656 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
1657 if (cif->chip_id != CHIP_RK3588_VEHICLE_CIF)
1658 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
1659 else
1660 csi2_dphy_write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
1661 } else {
1662 if (cif->chip_id <= CHIP_ID_RK3588) {
1663 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
1664 GENMASK(cif->cif_cfg.lanes - 1, 0));
1665 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
1666 } else {
1667 csi2_dphy_write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN,
1668 GENMASK(cif->cif_cfg.lanes - 1, 0));
1669 csi2_dphy_write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
1670 }
1671 if (cif->chip_id != CHIP_RK3588_VEHICLE_CIF)
1672 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
1673 else
1674 csi2_dphy_write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
1675 }
1676 }
1677
vehicle_csi2_dphy_stream_start(struct vehicle_cif * cif)1678 static int vehicle_csi2_dphy_stream_start(struct vehicle_cif *cif)
1679 {
1680 struct csi2_dphy_hw *hw = cif->dphy_hw;
1681 const struct hsfreq_range *hsfreq_ranges = hw->hsfreq_ranges;
1682 int num_hsfreq_ranges = hw->num_hsfreq_ranges;
1683 int i, hsfreq = 0;
1684 u32 val = 0, pre_val;
1685
1686
1687 mutex_lock(&hw->mutex);
1688
1689 /* set data lane num and enable clock lane */
1690 /*
1691 * for rk356x: dphy0 is used just for full mode,
1692 * dphy1 is used just for split mode,uses lane0_1,
1693 * dphy2 is used just for split mode,uses lane2_3
1694 */
1695 read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
1696 val |= (GENMASK(cif->cif_cfg.lanes - 1, 0) <<
1697 CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
1698 (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
1699
1700 val |= pre_val;
1701 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
1702
1703 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
1704 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
1705 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
1706 csi2_dphy_config_dual_mode(cif);
1707 }
1708
1709 /* not into receive mode/wait stopstate */
1710 csi2_dphy_write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
1711
1712 /* enable calibration */
1713 if (hw->data_rate_mbps > 1500) {
1714 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
1715 if (cif->cif_cfg.lanes > 0x00)
1716 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
1717 if (cif->cif_cfg.lanes > 0x01)
1718 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
1719 if (cif->cif_cfg.lanes > 0x02)
1720 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
1721 if (cif->cif_cfg.lanes > 0x03)
1722 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
1723 }
1724
1725 /* set clock lane and data lane */
1726 for (i = 0; i < num_hsfreq_ranges; i++) {
1727 if (hsfreq_ranges[i].range_h >= hw->data_rate_mbps) {
1728 hsfreq = hsfreq_ranges[i].cfg_bit;
1729 break;
1730 }
1731 }
1732
1733 if (i == num_hsfreq_ranges) {
1734 i = num_hsfreq_ranges - 1;
1735 dev_warn(hw->dev, "data rate: %lld mbps, max support %d mbps",
1736 hw->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1737 hsfreq = hsfreq_ranges[i].cfg_bit;
1738 }
1739
1740 VEHICLE_DG("mipi data_rate_mbps %lld, matched bit(0x%0x), lanes(%d)\n",
1741 hw->data_rate_mbps, hsfreq, cif->cif_cfg.lanes);
1742
1743 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
1744 if (cif->cif_cfg.lanes > 0x00)
1745 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
1746 if (cif->cif_cfg.lanes > 0x01)
1747 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
1748 if (cif->cif_cfg.lanes > 0x02)
1749 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
1750 if (cif->cif_cfg.lanes > 0x03)
1751 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
1752
1753 atomic_inc(&hw->stream_cnt);
1754
1755 mutex_unlock(&hw->mutex);
1756
1757 return 0;
1758 }
1759
vehicle_samsung_dcphy_rx_config_settle(struct vehicle_cif * cif)1760 static void vehicle_samsung_dcphy_rx_config_settle(struct vehicle_cif *cif)
1761 {
1762 struct csi2_dphy_hw *hw = cif->dphy_hw;
1763 struct samsung_mipi_dcphy *samsung = hw->samsung_phy;
1764 const struct hsfreq_range *hsfreq_ranges = NULL;
1765 int num_hsfreq_ranges = 0;
1766 int i, hsfreq = 0;
1767 u32 sot_sync = 0;
1768
1769 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
1770 hsfreq_ranges = hw->hsfreq_ranges;
1771 num_hsfreq_ranges = hw->num_hsfreq_ranges;
1772 sot_sync = 0x03;
1773 }
1774
1775 /* set data lane */
1776 for (i = 0; i < num_hsfreq_ranges; i++) {
1777 if (hsfreq_ranges[i].range_h >= hw->data_rate_mbps) {
1778 hsfreq = hsfreq_ranges[i].cfg_bit;
1779 break;
1780 }
1781 }
1782
1783 /*clk settle fix to 0x301*/
1784 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY)
1785 regmap_write(samsung->regmap, RX_CLK_THS_SETTLE, 0x301);
1786
1787 if (cif->cif_cfg.lanes > 0x00) {
1788 regmap_update_bits(samsung->regmap, RX_LANE0_THS_SETTLE, 0x1ff, hsfreq);
1789 regmap_update_bits(samsung->regmap, RX_LANE0_ERR_SOT_SYNC, 0xff, sot_sync);
1790 }
1791 if (cif->cif_cfg.lanes > 0x01) {
1792 regmap_update_bits(samsung->regmap, RX_LANE1_THS_SETTLE, 0x1ff, hsfreq);
1793 regmap_update_bits(samsung->regmap, RX_LANE1_ERR_SOT_SYNC, 0xff, sot_sync);
1794 }
1795 if (cif->cif_cfg.lanes > 0x02) {
1796 regmap_update_bits(samsung->regmap, RX_LANE2_THS_SETTLE, 0x1ff, hsfreq);
1797 regmap_update_bits(samsung->regmap, RX_LANE2_ERR_SOT_SYNC, 0xff, sot_sync);
1798 }
1799 if (cif->cif_cfg.lanes > 0x03) {
1800 regmap_update_bits(samsung->regmap, RX_LANE3_THS_SETTLE, 0x1ff, hsfreq);
1801 regmap_update_bits(samsung->regmap, RX_LANE3_ERR_SOT_SYNC, 0xff, sot_sync);
1802 }
1803 }
1804
vehicle_samsung_dcphy_rx_config_common(struct vehicle_cif * cif)1805 static int vehicle_samsung_dcphy_rx_config_common(struct vehicle_cif *cif)
1806 {
1807 struct csi2_dphy_hw *hw = cif->dphy_hw;
1808 struct samsung_mipi_dcphy *samsung = hw->samsung_phy;
1809 u32 dlysel = 0;
1810 int i = 0;
1811
1812 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
1813 if (hw->data_rate_mbps < 1500)
1814 dlysel = 0;
1815 else if (hw->data_rate_mbps < 2000)
1816 dlysel = 3 << 8;
1817 else if (hw->data_rate_mbps < 3000)
1818 dlysel = 2 << 8;
1819 else if (hw->data_rate_mbps < 4000)
1820 dlysel = 1 << 8;
1821 else if (hw->data_rate_mbps < 6500)
1822 dlysel = 0;
1823 if (hw->dphy_param->clk_hs_term_sel > 0x7) {
1824 dev_err(hw->dev, "clk_hs_term_sel error param %d\n",
1825 hw->dphy_param->clk_hs_term_sel);
1826 return -EINVAL;
1827 }
1828 for (i = 0; i < cif->cif_cfg.lanes; i++) {
1829 if (hw->dphy_param->data_hs_term_sel[i] > 0x7) {
1830 dev_err(hw->dev, "data_hs_term_sel[%d] error param %d\n",
1831 i,
1832 hw->dphy_param->data_hs_term_sel[i]);
1833 return -EINVAL;
1834 }
1835 if (hw->dphy_param->lp_hys_sw[i] > 0x3) {
1836 dev_err(hw->dev, "lp_hys_sw[%d] error param %d\n",
1837 i,
1838 hw->dphy_param->lp_hys_sw[i]);
1839 return -EINVAL;
1840 }
1841 if (hw->dphy_param->lp_escclk_pol_sel[i] > 0x1) {
1842 dev_err(hw->dev, "lp_escclk_pol_sel[%d] error param %d\n",
1843 i,
1844 hw->dphy_param->lp_escclk_pol_sel[i]);
1845 return -EINVAL;
1846 }
1847 if (hw->dphy_param->skew_data_cal_clk[i] > 0x1f) {
1848 dev_err(hw->dev, "skew_data_cal_clk[%d] error param %d\n",
1849 i,
1850 hw->dphy_param->skew_data_cal_clk[i]);
1851 return -EINVAL;
1852 }
1853 }
1854 regmap_write(samsung->regmap, RX_S0C_GNR_CON1, 0x1450);
1855 regmap_write(samsung->regmap, RX_S0C_ANA_CON1, 0x8000);
1856 regmap_write(samsung->regmap, RX_S0C_ANA_CON2, hw->dphy_param->clk_hs_term_sel);
1857 regmap_write(samsung->regmap, RX_S0C_ANA_CON3, 0x0600);
1858 if (cif->cif_cfg.lanes > 0x00) {
1859 regmap_write(samsung->regmap, RX_COMBO_S0D0_GNR_CON1, 0x1450);
1860 regmap_write(samsung->regmap, RX_COMBO_S0D0_ANA_CON1, 0x8000);
1861 regmap_write(samsung->regmap, RX_COMBO_S0D0_ANA_CON2, dlysel |
1862 hw->dphy_param->data_hs_term_sel[0]);
1863 regmap_write(samsung->regmap, RX_COMBO_S0D0_ANA_CON3, 0x0600 |
1864 (hw->dphy_param->lp_hys_sw[0] << 4) |
1865 (hw->dphy_param->lp_escclk_pol_sel[0] << 11));
1866 regmap_write(samsung->regmap, RX_COMBO_S0D0_ANA_CON7, 0x40);
1867 regmap_write(samsung->regmap, RX_COMBO_S0D0_DESKEW_CON2,
1868 hw->dphy_param->skew_data_cal_clk[0]);
1869 }
1870 if (cif->cif_cfg.lanes > 0x01) {
1871 regmap_write(samsung->regmap, RX_COMBO_S0D1_GNR_CON1, 0x1450);
1872 regmap_write(samsung->regmap, RX_COMBO_S0D1_ANA_CON1, 0x8000);
1873 regmap_write(samsung->regmap, RX_COMBO_S0D1_ANA_CON2, dlysel |
1874 hw->dphy_param->data_hs_term_sel[1]);
1875 regmap_write(samsung->regmap, RX_COMBO_S0D1_ANA_CON3, 0x0600 |
1876 (hw->dphy_param->lp_hys_sw[1] << 4) |
1877 (hw->dphy_param->lp_escclk_pol_sel[1] << 11));
1878 regmap_write(samsung->regmap, RX_COMBO_S0D1_ANA_CON7, 0x40);
1879 regmap_write(samsung->regmap, RX_COMBO_S0D1_DESKEW_CON2,
1880 hw->dphy_param->skew_data_cal_clk[1]);
1881 }
1882 if (cif->cif_cfg.lanes > 0x02) {
1883 regmap_write(samsung->regmap, RX_COMBO_S0D2_GNR_CON1, 0x1450);
1884 regmap_write(samsung->regmap, RX_COMBO_S0D2_ANA_CON1, 0x8000);
1885 regmap_write(samsung->regmap, RX_COMBO_S0D2_ANA_CON2, dlysel |
1886 hw->dphy_param->data_hs_term_sel[2]);
1887 regmap_write(samsung->regmap, RX_COMBO_S0D2_ANA_CON3, 0x0600 |
1888 (hw->dphy_param->lp_hys_sw[2] << 4) |
1889 (hw->dphy_param->lp_escclk_pol_sel[2] << 11));
1890 regmap_write(samsung->regmap, RX_COMBO_S0D2_ANA_CON7, 0x40);
1891 regmap_write(samsung->regmap, RX_COMBO_S0D2_DESKEW_CON2,
1892 hw->dphy_param->skew_data_cal_clk[2]);
1893 }
1894 if (cif->cif_cfg.lanes > 0x03) {
1895 regmap_write(samsung->regmap, RX_S0D3_GNR_CON1, 0x1450);
1896 regmap_write(samsung->regmap, RX_S0D3_ANA_CON1, 0x8000);
1897 regmap_write(samsung->regmap, RX_S0D3_ANA_CON2, dlysel |
1898 hw->dphy_param->data_hs_term_sel[3]);
1899 regmap_write(samsung->regmap, RX_S0D3_ANA_CON3, 0x0600 |
1900 (hw->dphy_param->lp_hys_sw[3] << 4) |
1901 (hw->dphy_param->lp_escclk_pol_sel[3] << 11));
1902 regmap_write(samsung->regmap, RX_S0D3_DESKEW_CON2,
1903 hw->dphy_param->skew_data_cal_clk[3]);
1904 }
1905 }
1906
1907 return 0;
1908 }
1909
vehicle_samsung_dcphy_rx_lane_enable(struct vehicle_cif * cif)1910 static int vehicle_samsung_dcphy_rx_lane_enable(struct vehicle_cif *cif)
1911 {
1912 struct csi2_dphy_hw *hw = cif->dphy_hw;
1913 struct samsung_mipi_dcphy *samsung = hw->samsung_phy;
1914 u32 sts;
1915 int ret = 0;
1916
1917 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY)
1918 regmap_update_bits(samsung->regmap, RX_CLK_LANE_ENABLE, PHY_ENABLE, PHY_ENABLE);
1919
1920 if (cif->cif_cfg.lanes > 0x00)
1921 regmap_update_bits(samsung->regmap, RX_DATA_LANE0_ENABLE, PHY_ENABLE, PHY_ENABLE);
1922 if (cif->cif_cfg.lanes > 0x01)
1923 regmap_update_bits(samsung->regmap, RX_DATA_LANE1_ENABLE, PHY_ENABLE, PHY_ENABLE);
1924 if (cif->cif_cfg.lanes > 0x02)
1925 regmap_update_bits(samsung->regmap, RX_DATA_LANE2_ENABLE, PHY_ENABLE, PHY_ENABLE);
1926 if (cif->cif_cfg.lanes > 0x03)
1927 regmap_update_bits(samsung->regmap, RX_DATA_LANE3_ENABLE, PHY_ENABLE, PHY_ENABLE);
1928
1929 /*wait for clk lane ready*/
1930 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
1931 ret = regmap_read_poll_timeout(samsung->regmap, RX_CLK_LANE_ENABLE,
1932 sts, (sts & PHY_READY), 200, 4000);
1933 if (ret < 0) {
1934 dev_err(samsung->dev, "phy rx clk lane is not locked\n");
1935 return -EINVAL;
1936 }
1937 }
1938
1939 /*wait for data lane ready*/
1940 if (cif->cif_cfg.lanes > 0x00) {
1941 ret = regmap_read_poll_timeout(samsung->regmap, RX_DATA_LANE0_ENABLE,
1942 sts, (sts & PHY_READY), 200, 2000);
1943 if (ret < 0) {
1944 dev_err(samsung->dev, "phy rx data lane 0 is not locked\n");
1945 return -EINVAL;
1946 }
1947 }
1948 if (cif->cif_cfg.lanes > 0x01) {
1949 ret = regmap_read_poll_timeout(samsung->regmap, RX_DATA_LANE1_ENABLE,
1950 sts, (sts & PHY_READY), 200, 2000);
1951 if (ret < 0) {
1952 dev_err(samsung->dev, "phy rx data lane 1 is not locked\n");
1953 return -EINVAL;
1954 }
1955 }
1956 if (cif->cif_cfg.lanes > 0x02) {
1957 ret = regmap_read_poll_timeout(samsung->regmap, RX_DATA_LANE2_ENABLE,
1958 sts, (sts & PHY_READY), 200, 2000);
1959 if (ret < 0) {
1960 dev_err(samsung->dev, "phy rx data lane 2 is not locked\n");
1961 return -EINVAL;
1962 }
1963 }
1964
1965 if (cif->cif_cfg.lanes > 0x03) {
1966 ret = regmap_read_poll_timeout(samsung->regmap, RX_DATA_LANE3_ENABLE,
1967 sts, (sts & PHY_READY), 200, 2000);
1968 if (ret < 0) {
1969 dev_err(samsung->dev, "phy rx data lane 3 is not locked\n");
1970 return -EINVAL;
1971 }
1972 }
1973 return 0;
1974 }
1975
vehicle_samsung_mipi_dcphy_bias_block_enable(struct vehicle_cif * cif)1976 static void vehicle_samsung_mipi_dcphy_bias_block_enable(struct vehicle_cif *cif)
1977 {
1978 struct csi2_dphy_hw *hw = cif->dphy_hw;
1979 struct samsung_mipi_dcphy *samsung = hw->samsung_phy;
1980 struct csi2_dphy_hw *csi_dphy = samsung->dphy_vehicle[0];
1981 u32 bias_con2 = 0x3223;
1982
1983 if (csi_dphy &&
1984 csi_dphy->dphy_param->lp_vol_ref != 3 &&
1985 csi_dphy->dphy_param->lp_vol_ref < 0x7) {
1986 bias_con2 &= 0xfffffff8;
1987 bias_con2 |= csi_dphy->dphy_param->lp_vol_ref;
1988 dev_info(samsung->dev,
1989 "rx change lp_vol_ref to %d, it may cause tx exception\n",
1990 csi_dphy->dphy_param->lp_vol_ref);
1991 }
1992 regmap_write(samsung->regmap, BIAS_CON0, 0x0010);
1993 regmap_write(samsung->regmap, BIAS_CON1, 0x0110);
1994 regmap_write(samsung->regmap, BIAS_CON2, bias_con2);
1995
1996 /* default output voltage select:
1997 * dphy: 400mv
1998 * cphy: 530mv
1999 */
2000 if (samsung->c_option)
2001 regmap_update_bits(samsung->regmap, BIAS_CON4,
2002 I_MUX_SEL_MASK, I_MUX_SEL(2));
2003 }
2004
vehicle_csi2_dcphy_stream_start(struct vehicle_cif * cif)2005 static int vehicle_csi2_dcphy_stream_start(struct vehicle_cif *cif)
2006 {
2007 struct csi2_dphy_hw *hw = cif->dphy_hw;
2008 struct samsung_mipi_dcphy *samsung = hw->samsung_phy;
2009 int ret = 0;
2010
2011 dev_info(hw->dev, "mipi dcphy stream on\n");
2012 mutex_lock(&hw->mutex);
2013
2014 if (samsung->s_phy_rst)
2015 reset_control_assert(samsung->s_phy_rst);
2016
2017 vehicle_samsung_mipi_dcphy_bias_block_enable(cif);
2018 ret = vehicle_samsung_dcphy_rx_config_common(cif);
2019 if (ret)
2020 goto out_streamon;
2021
2022 vehicle_samsung_dcphy_rx_config_settle(cif);
2023
2024 ret = vehicle_samsung_dcphy_rx_lane_enable(cif);
2025 if (ret)
2026 goto out_streamon;
2027
2028 if (samsung->s_phy_rst)
2029 reset_control_deassert(samsung->s_phy_rst);
2030 atomic_inc(&hw->stream_cnt);
2031 mutex_unlock(&hw->mutex);
2032
2033 return 0;
2034
2035 out_streamon:
2036 if (samsung->s_phy_rst)
2037 reset_control_deassert(samsung->s_phy_rst);
2038 mutex_unlock(&hw->mutex);
2039 dev_err(hw->dev, "stream on error\n");
2040 return -EINVAL;
2041 }
2042
vehicle_csi2_dcphy_stream_stop(struct vehicle_cif * cif)2043 static int vehicle_csi2_dcphy_stream_stop(struct vehicle_cif *cif)
2044 {
2045 struct csi2_dphy_hw *hw = cif->dphy_hw;
2046 struct samsung_mipi_dcphy *samsung = hw->samsung_phy;
2047
2048 dev_info(hw->dev, "mipi dcphy stream off\n");
2049 if (atomic_dec_return(&hw->stream_cnt))
2050 return 0;
2051
2052 mutex_lock(&hw->mutex);
2053
2054 if (samsung->s_phy_rst)
2055 reset_control_assert(samsung->s_phy_rst);
2056 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY)
2057 regmap_update_bits(samsung->regmap, RX_CLK_LANE_ENABLE, PHY_ENABLE, 0);
2058
2059 if (cif->cif_cfg.lanes > 0x00)
2060 regmap_update_bits(samsung->regmap, RX_DATA_LANE0_ENABLE, PHY_ENABLE, 0);
2061 if (cif->cif_cfg.lanes > 0x01)
2062 regmap_update_bits(samsung->regmap, RX_DATA_LANE1_ENABLE, PHY_ENABLE, 0);
2063 if (cif->cif_cfg.lanes > 0x02)
2064 regmap_update_bits(samsung->regmap, RX_DATA_LANE2_ENABLE, PHY_ENABLE, 0);
2065 if (cif->cif_cfg.lanes > 0x03)
2066 regmap_update_bits(samsung->regmap, RX_DATA_LANE3_ENABLE, PHY_ENABLE, 0);
2067
2068 if (samsung->s_phy_rst)
2069 reset_control_deassert(samsung->s_phy_rst);
2070 usleep_range(500, 1000);
2071
2072 mutex_unlock(&hw->mutex);
2073
2074 return 0;
2075 }
2076
vehicle_csi2_disable(struct vehicle_cif * cif)2077 static void vehicle_csi2_disable(struct vehicle_cif *cif)
2078 {
2079 void __iomem *base = cif->csi2_base;
2080
2081 vehicle_write_csihost_reg(base, CSIHOST_RESETN, 0);
2082 vehicle_write_csihost_reg(base, CSIHOST_MSK1, 0xffffffff);
2083 vehicle_write_csihost_reg(base, CSIHOST_MSK2, 0xffffffff);
2084 }
2085
vehicle_csi2_enable(struct vehicle_cif * cif,enum host_type_t host_type)2086 static void vehicle_csi2_enable(struct vehicle_cif *cif,
2087 enum host_type_t host_type)
2088 {
2089 struct csi2_dphy_hw *hw = cif->dphy_hw;
2090 void __iomem *base = hw->csi2_base;
2091 int lanes = cif->cif_cfg.lanes;
2092
2093 vehicle_write_csihost_reg(base, CSIHOST_N_LANES, lanes - 1);
2094
2095 if (host_type == RK_DSI_RXHOST) {
2096 vehicle_write_csihost_reg(base, CSIHOST_CONTROL,
2097 SW_CPHY_EN(0) | SW_DSI_EN(1) |
2098 SW_DATATYPE_FS(0x01) | SW_DATATYPE_FE(0x11) |
2099 SW_DATATYPE_LS(0x21) | SW_DATATYPE_LE(0x31));
2100 /* Disable some error interrupt when HOST work on DSI RX mode */
2101 vehicle_write_csihost_reg(base, CSIHOST_MSK1, 0xe00000f0);
2102 vehicle_write_csihost_reg(base, CSIHOST_MSK2, 0xff00);
2103 } else {
2104 vehicle_write_csihost_reg(base, CSIHOST_CONTROL,
2105 SW_CPHY_EN(0) | SW_DSI_EN(0) |
2106 SW_DATATYPE_FS(0x0) | SW_DATATYPE_FE(0x01) |
2107 SW_DATATYPE_LS(0x02) | SW_DATATYPE_LE(0x03));
2108 vehicle_write_csihost_reg(base, CSIHOST_MSK1, 0);
2109 vehicle_write_csihost_reg(base, CSIHOST_MSK2, 0xf000);
2110 }
2111
2112 vehicle_write_csihost_reg(base, CSIHOST_RESETN, 1);
2113 }
2114
vehicle_csi2_stream_start(struct vehicle_cif * cif)2115 static int vehicle_csi2_stream_start(struct vehicle_cif *cif)
2116 {
2117 struct csi2_dphy_hw *hw = cif->dphy_hw;
2118 enum host_type_t host_type;
2119 int i;
2120
2121 host_type = RK_CSI_RXHOST;
2122 vehicle_csi2_enable(cif, host_type);
2123 for (i = 0; i < RK_CSI2_ERR_MAX; i++)
2124 hw->err_list[i].cnt = 0;
2125
2126 return 0;
2127 }
2128
vehicle_cif_csi_get_vc_num(struct vehicle_cif * cif)2129 static void vehicle_cif_csi_get_vc_num(struct vehicle_cif *cif)
2130 {
2131 int vc_num = 0;
2132 unsigned int mbus_flags = cif->cif_cfg.mbus_flags;
2133
2134 for (vc_num = 0; vc_num < RKCIF_MAX_CSI_CHANNEL; vc_num++) {
2135 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_0) {
2136 cif->channels[vc_num].vc = vc_num;
2137 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_0;
2138 continue;
2139 }
2140 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_1) {
2141 cif->channels[vc_num].vc = vc_num;
2142 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_1;
2143 continue;
2144 }
2145
2146 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_2) {
2147 cif->channels[vc_num].vc = vc_num;
2148 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_2;
2149 continue;
2150 }
2151
2152 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_3) {
2153 cif->channels[vc_num].vc = vc_num;
2154 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_3;
2155 continue;
2156 }
2157 }
2158
2159 cif->num_channels = vc_num ? (vc_num - 1) : 1;
2160 if (cif->num_channels == 1)
2161 cif->channels[0].vc = 0;
2162 }
2163
2164 static const struct
find_input_fmt(u32 mbus_code)2165 cif_input_fmt *find_input_fmt(u32 mbus_code)
2166 {
2167 const struct cif_input_fmt *fmt;
2168 u32 i;
2169
2170 for (i = 0; i < ARRAY_SIZE(in_fmts); i++) {
2171 fmt = &in_fmts[i];
2172 if (mbus_code == fmt->mbus_code)
2173 return fmt;
2174 }
2175
2176 return NULL;
2177 }
2178
2179 static const struct
find_output_fmt(u32 pixelfmt)2180 cif_output_fmt *find_output_fmt(u32 pixelfmt)
2181 {
2182 const struct cif_output_fmt *fmt;
2183 u32 i;
2184
2185 for (i = 0; i < ARRAY_SIZE(out_fmts); i++) {
2186 fmt = &out_fmts[i];
2187 if (fmt->fourcc == pixelfmt)
2188 return fmt;
2189 }
2190
2191 return NULL;
2192 }
2193
get_reg_index_of_id_ctrl0(int channel_id)2194 static enum cif_reg_index get_reg_index_of_id_ctrl0(int channel_id)
2195 {
2196 enum cif_reg_index index;
2197
2198 switch (channel_id) {
2199 case 0:
2200 index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
2201 break;
2202 case 1:
2203 index = CIF_REG_MIPI_LVDS_ID1_CTRL0;
2204 break;
2205 case 2:
2206 index = CIF_REG_MIPI_LVDS_ID2_CTRL0;
2207 break;
2208 case 3:
2209 index = CIF_REG_MIPI_LVDS_ID3_CTRL0;
2210 break;
2211 default:
2212 index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
2213 break;
2214 }
2215
2216 return index;
2217 }
2218
get_reg_index_of_id_ctrl1(int channel_id)2219 static enum cif_reg_index get_reg_index_of_id_ctrl1(int channel_id)
2220 {
2221 enum cif_reg_index index;
2222
2223 switch (channel_id) {
2224 case 0:
2225 index = CIF_REG_MIPI_LVDS_ID0_CTRL1;
2226 break;
2227 case 1:
2228 index = CIF_REG_MIPI_LVDS_ID1_CTRL1;
2229 break;
2230 case 2:
2231 index = CIF_REG_MIPI_LVDS_ID2_CTRL1;
2232 break;
2233 case 3:
2234 index = CIF_REG_MIPI_LVDS_ID3_CTRL1;
2235 break;
2236 default:
2237 index = CIF_REG_MIPI_LVDS_ID0_CTRL1;
2238 break;
2239 }
2240
2241 return index;
2242 }
2243
get_reg_index_of_frm0_y_addr(int channel_id)2244 static enum cif_reg_index get_reg_index_of_frm0_y_addr(int channel_id)
2245 {
2246 enum cif_reg_index index;
2247
2248 switch (channel_id) {
2249 case 0:
2250 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0;
2251 break;
2252 case 1:
2253 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1;
2254 break;
2255 case 2:
2256 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2;
2257 break;
2258 case 3:
2259 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3;
2260 break;
2261 default:
2262 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0;
2263 break;
2264 }
2265
2266 return index;
2267 }
2268
get_reg_index_of_frm_num(int channel_id)2269 static enum cif_reg_index get_reg_index_of_frm_num(int channel_id)
2270 {
2271 enum cif_reg_index index;
2272
2273 switch (channel_id) {
2274 case 0:
2275 index = CIF_REG_MIPI_FRAME_NUM_VC0;
2276 break;
2277 case 1:
2278 index = CIF_REG_MIPI_FRAME_NUM_VC1;
2279 break;
2280 case 2:
2281 index = CIF_REG_MIPI_FRAME_NUM_VC2;
2282 break;
2283 case 3:
2284 index = CIF_REG_MIPI_FRAME_NUM_VC3;
2285 break;
2286 default:
2287 index = CIF_REG_MIPI_FRAME_NUM_VC0;
2288 break;
2289 }
2290
2291 return index;
2292 }
2293
get_reg_index_of_frm1_y_addr(int channel_id)2294 static enum cif_reg_index get_reg_index_of_frm1_y_addr(int channel_id)
2295 {
2296 enum cif_reg_index index;
2297
2298 switch (channel_id) {
2299 case 0:
2300 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0;
2301 break;
2302 case 1:
2303 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1;
2304 break;
2305 case 2:
2306 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2;
2307 break;
2308 case 3:
2309 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3;
2310 break;
2311 default:
2312 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0;
2313 break;
2314 }
2315
2316 return index;
2317 }
2318
get_reg_index_of_frm0_uv_addr(int channel_id)2319 static enum cif_reg_index get_reg_index_of_frm0_uv_addr(int channel_id)
2320 {
2321 enum cif_reg_index index;
2322
2323 switch (channel_id) {
2324 case 0:
2325 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0;
2326 break;
2327 case 1:
2328 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1;
2329 break;
2330 case 2:
2331 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2;
2332 break;
2333 case 3:
2334 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3;
2335 break;
2336 default:
2337 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0;
2338 break;
2339 }
2340
2341 return index;
2342 }
2343
get_reg_index_of_frm1_uv_addr(int channel_id)2344 static enum cif_reg_index get_reg_index_of_frm1_uv_addr(int channel_id)
2345 {
2346 enum cif_reg_index index;
2347
2348 switch (channel_id) {
2349 case 0:
2350 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0;
2351 break;
2352 case 1:
2353 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1;
2354 break;
2355 case 2:
2356 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2;
2357 break;
2358 case 3:
2359 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3;
2360 break;
2361 default:
2362 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0;
2363 break;
2364 }
2365
2366 return index;
2367 }
2368
get_reg_index_of_frm0_y_vlw(int channel_id)2369 static enum cif_reg_index get_reg_index_of_frm0_y_vlw(int channel_id)
2370 {
2371 enum cif_reg_index index;
2372
2373 switch (channel_id) {
2374 case 0:
2375 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0;
2376 break;
2377 case 1:
2378 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1;
2379 break;
2380 case 2:
2381 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2;
2382 break;
2383 case 3:
2384 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3;
2385 break;
2386 default:
2387 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0;
2388 break;
2389 }
2390
2391 return index;
2392 }
2393
get_reg_index_of_frm1_y_vlw(int channel_id)2394 static enum cif_reg_index get_reg_index_of_frm1_y_vlw(int channel_id)
2395 {
2396 enum cif_reg_index index;
2397
2398 switch (channel_id) {
2399 case 0:
2400 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0;
2401 break;
2402 case 1:
2403 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1;
2404 break;
2405 case 2:
2406 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2;
2407 break;
2408 case 3:
2409 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3;
2410 break;
2411 default:
2412 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0;
2413 break;
2414 }
2415
2416 return index;
2417 }
2418
get_reg_index_of_frm0_uv_vlw(int channel_id)2419 static enum cif_reg_index get_reg_index_of_frm0_uv_vlw(int channel_id)
2420 {
2421 enum cif_reg_index index;
2422
2423 switch (channel_id) {
2424 case 0:
2425 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0;
2426 break;
2427 case 1:
2428 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1;
2429 break;
2430 case 2:
2431 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2;
2432 break;
2433 case 3:
2434 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3;
2435 break;
2436 default:
2437 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0;
2438 break;
2439 }
2440
2441 return index;
2442 }
2443
get_reg_index_of_frm1_uv_vlw(int channel_id)2444 static enum cif_reg_index get_reg_index_of_frm1_uv_vlw(int channel_id)
2445 {
2446 enum cif_reg_index index;
2447
2448 switch (channel_id) {
2449 case 0:
2450 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0;
2451 break;
2452 case 1:
2453 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1;
2454 break;
2455 case 2:
2456 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2;
2457 break;
2458 case 3:
2459 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3;
2460 break;
2461 default:
2462 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0;
2463 break;
2464 }
2465
2466 return index;
2467 }
2468
get_reg_index_of_id_crop_start(int channel_id)2469 static enum cif_reg_index get_reg_index_of_id_crop_start(int channel_id)
2470 {
2471 enum cif_reg_index index;
2472
2473 switch (channel_id) {
2474 case 0:
2475 index = CIF_REG_MIPI_LVDS_ID0_CROP_START;
2476 break;
2477 case 1:
2478 index = CIF_REG_MIPI_LVDS_ID1_CROP_START;
2479 break;
2480 case 2:
2481 index = CIF_REG_MIPI_LVDS_ID2_CROP_START;
2482 break;
2483 case 3:
2484 index = CIF_REG_MIPI_LVDS_ID3_CROP_START;
2485 break;
2486 default:
2487 index = CIF_REG_MIPI_LVDS_ID0_CROP_START;
2488 break;
2489 }
2490
2491 return index;
2492 }
2493
get_dvp_reg_index_of_frm0_y_addr(int channel_id)2494 static enum cif_reg_index get_dvp_reg_index_of_frm0_y_addr(int channel_id)
2495 {
2496 enum cif_reg_index index;
2497
2498 switch (channel_id) {
2499 case 0:
2500 index = CIF_REG_DVP_FRM0_ADDR_Y;
2501 break;
2502 case 1:
2503 index = CIF_REG_DVP_FRM0_ADDR_Y_ID1;
2504 break;
2505 case 2:
2506 index = CIF_REG_DVP_FRM0_ADDR_Y_ID2;
2507 break;
2508 case 3:
2509 index = CIF_REG_DVP_FRM0_ADDR_Y_ID3;
2510 break;
2511 default:
2512 index = CIF_REG_DVP_FRM0_ADDR_Y;
2513 break;
2514 }
2515
2516 return index;
2517 }
2518
get_dvp_reg_index_of_frm1_y_addr(int channel_id)2519 static enum cif_reg_index get_dvp_reg_index_of_frm1_y_addr(int channel_id)
2520 {
2521 enum cif_reg_index index;
2522
2523 switch (channel_id) {
2524 case 0:
2525 index = CIF_REG_DVP_FRM1_ADDR_Y;
2526 break;
2527 case 1:
2528 index = CIF_REG_DVP_FRM1_ADDR_Y_ID1;
2529 break;
2530 case 2:
2531 index = CIF_REG_DVP_FRM1_ADDR_Y_ID2;
2532 break;
2533 case 3:
2534 index = CIF_REG_DVP_FRM1_ADDR_Y_ID3;
2535 break;
2536 default:
2537 index = CIF_REG_DVP_FRM0_ADDR_Y;
2538 break;
2539 }
2540
2541 return index;
2542 }
2543
get_dvp_reg_index_of_frm0_uv_addr(int channel_id)2544 static enum cif_reg_index get_dvp_reg_index_of_frm0_uv_addr(int channel_id)
2545 {
2546 enum cif_reg_index index;
2547
2548 switch (channel_id) {
2549 case 0:
2550 index = CIF_REG_DVP_FRM0_ADDR_UV;
2551 break;
2552 case 1:
2553 index = CIF_REG_DVP_FRM0_ADDR_UV_ID1;
2554 break;
2555 case 2:
2556 index = CIF_REG_DVP_FRM0_ADDR_UV_ID2;
2557 break;
2558 case 3:
2559 index = CIF_REG_DVP_FRM0_ADDR_UV_ID3;
2560 break;
2561 default:
2562 index = CIF_REG_DVP_FRM0_ADDR_UV;
2563 break;
2564 }
2565
2566 return index;
2567 }
2568
get_dvp_reg_index_of_frm1_uv_addr(int channel_id)2569 static enum cif_reg_index get_dvp_reg_index_of_frm1_uv_addr(int channel_id)
2570 {
2571 enum cif_reg_index index;
2572
2573 switch (channel_id) {
2574 case 0:
2575 index = CIF_REG_DVP_FRM1_ADDR_UV;
2576 break;
2577 case 1:
2578 index = CIF_REG_DVP_FRM1_ADDR_UV_ID1;
2579 break;
2580 case 2:
2581 index = CIF_REG_DVP_FRM1_ADDR_UV_ID2;
2582 break;
2583 case 3:
2584 index = CIF_REG_DVP_FRM1_ADDR_UV_ID3;
2585 break;
2586 default:
2587 index = CIF_REG_DVP_FRM1_ADDR_UV;
2588 break;
2589 }
2590
2591 return index;
2592 }
2593
get_data_type(u32 pixelformat,u8 cmd_mode_en)2594 static unsigned char get_data_type(u32 pixelformat, u8 cmd_mode_en)
2595 {
2596 switch (pixelformat) {
2597 /* csi raw8 */
2598 case MEDIA_BUS_FMT_SBGGR8_1X8:
2599 case MEDIA_BUS_FMT_SGBRG8_1X8:
2600 case MEDIA_BUS_FMT_SGRBG8_1X8:
2601 case MEDIA_BUS_FMT_SRGGB8_1X8:
2602 return 0x2a;
2603 /* csi raw10 */
2604 case MEDIA_BUS_FMT_SBGGR10_1X10:
2605 case MEDIA_BUS_FMT_SGBRG10_1X10:
2606 case MEDIA_BUS_FMT_SGRBG10_1X10:
2607 case MEDIA_BUS_FMT_SRGGB10_1X10:
2608 return 0x2b;
2609 /* csi raw12 */
2610 case MEDIA_BUS_FMT_SBGGR12_1X12:
2611 case MEDIA_BUS_FMT_SGBRG12_1X12:
2612 case MEDIA_BUS_FMT_SGRBG12_1X12:
2613 case MEDIA_BUS_FMT_SRGGB12_1X12:
2614 return 0x2c;
2615 /* csi uyvy 422 */
2616 case MEDIA_BUS_FMT_UYVY8_2X8:
2617 case MEDIA_BUS_FMT_VYUY8_2X8:
2618 case MEDIA_BUS_FMT_YUYV8_2X8:
2619 case MEDIA_BUS_FMT_YVYU8_2X8:
2620 return 0x1e;
2621 case MEDIA_BUS_FMT_RGB888_1X24: {
2622 if (cmd_mode_en) /* dsi command mode*/
2623 return 0x39;
2624 else /* dsi video mode */
2625 return 0x3e;
2626 }
2627
2628 default:
2629 return 0x2b;
2630 }
2631 }
2632
2633 #define UV_OFFSET (cif->cif_cfg.width * cif->cif_cfg.height)
2634
vehicle_cif_init_buffer(struct vehicle_cif * cif,int init,int csi_ch)2635 static int vehicle_cif_init_buffer(struct vehicle_cif *cif,
2636 int init, int csi_ch)
2637 {
2638 struct vehicle_rkcif_dummy_buffer *dummy_buf = &cif->dummy_buf;
2639 u32 frm0_addr_y, frm0_addr_uv;
2640 u32 frm1_addr_y, frm1_addr_uv;
2641 unsigned long y_addr, uv_addr;
2642 int i;
2643
2644 if (cif->cif_cfg.buf_num < 2)
2645 return -EINVAL;
2646
2647 if (cif->cif_cfg.buf_num > MAX_BUF_NUM)
2648 cif->cif_cfg.buf_num = MAX_BUF_NUM;
2649
2650 for (i = 0 ; i < cif->cif_cfg.buf_num; i++) {
2651 cif->frame_buf[i] = cif->cif_cfg.buf_phy_addr[i];
2652 if (cif->frame_buf[i] == 0)
2653 return -EINVAL;
2654 }
2655
2656 cif->last_buf_index = 0;
2657 cif->current_buf_index = 1;
2658
2659 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
2660 frm0_addr_y = get_reg_index_of_frm0_y_addr(csi_ch);
2661 frm0_addr_uv = get_reg_index_of_frm0_uv_addr(csi_ch);
2662 frm1_addr_y = get_reg_index_of_frm1_y_addr(csi_ch);
2663 frm1_addr_uv = get_reg_index_of_frm1_uv_addr(csi_ch);
2664 } else {
2665 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(csi_ch);
2666 frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(csi_ch);
2667 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(csi_ch);
2668 frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(csi_ch);
2669 }
2670
2671 spin_lock(&cif->vbq_lock);
2672
2673 y_addr = vehicle_flinger_request_cif_buffer();
2674 if (y_addr) {
2675 uv_addr = y_addr + UV_OFFSET;
2676 rkcif_write_reg(cif, frm0_addr_y, y_addr);
2677 rkcif_write_reg(cif, frm0_addr_uv, uv_addr);
2678 cif->active[0] = y_addr;
2679 } else {
2680 rkcif_write_reg(cif, frm0_addr_y, dummy_buf->dma_addr);
2681 rkcif_write_reg(cif, frm0_addr_uv, dummy_buf->dma_addr);
2682 cif->active[0] = y_addr;
2683 }
2684
2685 y_addr = vehicle_flinger_request_cif_buffer();
2686 if (y_addr) {
2687 uv_addr = y_addr + UV_OFFSET;
2688 rkcif_write_reg(cif, frm1_addr_y, y_addr);
2689 rkcif_write_reg(cif, frm1_addr_uv, uv_addr);
2690 cif->active[1] = y_addr;
2691 } else {
2692 rkcif_write_reg(cif, frm1_addr_y, dummy_buf->dma_addr);
2693 rkcif_write_reg(cif, frm1_addr_uv, dummy_buf->dma_addr);
2694 cif->active[1] = y_addr;
2695 }
2696
2697 if (cif->cif_cfg.type != V4L2_MBUS_CSI2_DPHY) {
2698 int ch_id;
2699
2700 for (ch_id = 0; ch_id < 4; ch_id++) {
2701 if (ch_id == csi_ch)
2702 continue;
2703
2704 rkcif_write_reg(cif, get_dvp_reg_index_of_frm0_y_addr(ch_id),
2705 dummy_buf->dma_addr);
2706 rkcif_write_reg(cif, get_dvp_reg_index_of_frm1_y_addr(ch_id),
2707 dummy_buf->dma_addr);
2708 rkcif_write_reg(cif, get_dvp_reg_index_of_frm0_uv_addr(ch_id),
2709 dummy_buf->dma_addr);
2710 rkcif_write_reg(cif, get_dvp_reg_index_of_frm1_uv_addr(ch_id),
2711 dummy_buf->dma_addr);
2712 }
2713 }
2714
2715 spin_unlock(&cif->vbq_lock);
2716
2717 return 0;
2718 }
2719
vehicle_cif_csi_channel_init(struct vehicle_cif * cif,struct vehicle_csi_channel_info * channel)2720 static int vehicle_cif_csi_channel_init(struct vehicle_cif *cif,
2721 struct vehicle_csi_channel_info *channel)
2722 {
2723 struct vehicle_cfg *cfg = &cif->cif_cfg;
2724 const struct cif_output_fmt *fmt;
2725 u32 fourcc;
2726
2727 channel->enable = 1;
2728 channel->width = cfg->width;
2729 channel->height = cfg->height;
2730 cif->interlaced_enable = false;
2731 channel->cmd_mode_en = 0; /* default use DSI Video Mode */
2732
2733 channel->crop_en = 1;
2734 channel->crop_st_x = cfg->start_x;
2735 channel->crop_st_y = cfg->start_y;
2736 channel->width = cfg->width;
2737 channel->height = cfg->height;
2738 if (cfg->output_format == CIF_OUTPUT_FORMAT_420) {
2739 fmt = find_output_fmt(V4L2_PIX_FMT_NV12);
2740 if (!fmt) {
2741 VEHICLE_DGERR("can not find output format: 0x%x", V4L2_PIX_FMT_NV12);
2742 return -EINVAL;
2743 }
2744 } else {
2745 fmt = find_output_fmt(V4L2_PIX_FMT_NV16);
2746 if (!fmt) {
2747 VEHICLE_DGERR("can not find output format: 0x%x", V4L2_PIX_FMT_NV16);
2748 return -EINVAL;
2749 }
2750 }
2751 // channel->fmt_val = fmt->csi_fmt_val;
2752 /* set cif input format yuv422*/
2753 channel->fmt_val = CSI_WRDDR_TYPE_YUV422;
2754 VEHICLE_INFO("%s, LINE=%d, channel->fmt_val = 0x%x, fmt->csi_fmt_val= 0x%x",
2755 __func__, __LINE__, channel->fmt_val, fmt->csi_fmt_val);
2756 /*
2757 * for mipi or lvds, when enable compact, the virtual width of raw10/raw12
2758 * needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
2759 * needs aligned with :ALIGN(bits_per_pixel * width * 2, 8), to optimize reading and
2760 * writing of ddr, aligned with 256
2761 */
2762
2763 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && channel->fmt_val != CSI_WRDDR_TYPE_RAW8)
2764 channel->virtual_width = ALIGN(channel->width * 2, 8);
2765 else
2766 channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
2767
2768 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
2769 channel->width = channel->width * fmt->bpp[0] / 8;
2770 /*
2771 * rk cif don't support output yuyv fmt data
2772 * if user request yuyv fmt, the input mode must be RAW8
2773 * and the width is double Because the real input fmt is
2774 * yuyv
2775 */
2776 fourcc = fmt->fourcc;
2777 if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
2778 fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY) {
2779 channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
2780 channel->width *= 2;
2781 channel->virtual_width *= 2;
2782 }
2783 VEHICLE_DG("%s, LINE=%d, channel->fmt_val = 0x%x", __func__, __LINE__, channel->fmt_val);
2784 if (cfg->input_format == CIF_INPUT_FORMAT_PAL ||
2785 cfg->input_format == CIF_INPUT_FORMAT_NTSC) {
2786 VEHICLE_INFO("CVBS IN PAL or NTSC config.");
2787 channel->virtual_width *= 2;
2788 cif->interlaced_enable = true;
2789 cif->interlaced_offset = channel->width;
2790 cif->interlaced_counts = 0;
2791 cif->interlaced_buffer = 0;
2792 channel->height /= 2;
2793 VEHICLE_INFO("do denterlaced.\n");
2794 }
2795
2796 channel->data_type = get_data_type(cfg->mbus_code,
2797 channel->cmd_mode_en);
2798
2799 return 0;
2800 }
2801
vehicle_cif_csi_channel_set(struct vehicle_cif * cif,struct vehicle_csi_channel_info * channel,enum v4l2_mbus_type mbus_type)2802 static int vehicle_cif_csi_channel_set(struct vehicle_cif *cif,
2803 struct vehicle_csi_channel_info *channel,
2804 enum v4l2_mbus_type mbus_type)
2805
2806 {
2807 unsigned int val = 0x0;
2808
2809 if (channel->id >= 4)
2810 return -EINVAL;
2811
2812 if (!channel->enable) {
2813 rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id),
2814 CSI_DISABLE_CAPTURE);
2815 return 0;
2816 }
2817
2818 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTSTAT,
2819 ~(CSI_START_INTSTAT(channel->id) |
2820 CSI_DMA_END_INTSTAT(channel->id) |
2821 CSI_LINE_INTSTAT(channel->id)));
2822
2823 /* 0. need set CIF_CSI_INTEN to 0x0 first */
2824 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTEN, 0x0);
2825
2826 /* enable id0 frame start int for sof(long frame, for hdr)
2827 * vehicle don't need this
2828 */
2829 if (channel->id == RKCIF_STREAM_MIPI_ID0)
2830 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTEN,
2831 CSI_START_INTEN(channel->id));
2832
2833 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
2834 0x3fff << 16 | 0x3fff);
2835 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
2836 0x3fff << 16 | 0x3fff);
2837
2838 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTEN,
2839 CSI_DMA_END_INTEN(channel->id));
2840
2841 rkcif_write_reg(cif, CIF_REG_MIPI_WATER_LINE,
2842 CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 |
2843 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808 |
2844 CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(0x3) |
2845 CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808);
2846
2847 val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x3) |
2848 CIF_MIPI_LVDS_SW_PRESS_ENABLE |
2849 CIF_MIPI_LVDS_SW_HURRY_VALUE(0x3) |
2850 CIF_MIPI_LVDS_SW_HURRY_ENABLE |
2851 CIF_MIPI_LVDS_SW_WATER_LINE_25 |
2852 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
2853
2854 val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
2855
2856 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_CTRL, val);
2857
2858 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTEN,
2859 CSI_ALL_ERROR_INTEN);
2860
2861 rkcif_write_reg(cif, get_reg_index_of_id_ctrl1(channel->id),
2862 channel->width | (channel->height << 16));
2863
2864 rkcif_write_reg(cif, get_reg_index_of_frm0_y_vlw(channel->id),
2865 channel->virtual_width);
2866 rkcif_write_reg(cif, get_reg_index_of_frm1_y_vlw(channel->id),
2867 channel->virtual_width);
2868 rkcif_write_reg(cif, get_reg_index_of_frm0_uv_vlw(channel->id),
2869 channel->virtual_width);
2870 rkcif_write_reg(cif, get_reg_index_of_frm1_uv_vlw(channel->id),
2871 channel->virtual_width);
2872
2873 if (channel->crop_en)
2874 rkcif_write_reg(cif, get_reg_index_of_id_crop_start(channel->id),
2875 channel->crop_st_y << 16 | channel->crop_st_x);
2876
2877 return 0;
2878 }
2879
2880 /*config reg for rk3588*/
vehicle_cif_csi_channel_set_v1(struct vehicle_cif * cif,struct vehicle_csi_channel_info * channel,enum v4l2_mbus_type mbus_type)2881 static int vehicle_cif_csi_channel_set_v1(struct vehicle_cif *cif,
2882 struct vehicle_csi_channel_info *channel,
2883 enum v4l2_mbus_type mbus_type)
2884 {
2885 unsigned int val = 0x0;
2886
2887 if (channel->id >= 4)
2888 return -EINVAL;
2889
2890 if (!channel->enable) {
2891 rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id),
2892 CSI_DISABLE_CAPTURE);
2893 return 0;
2894 }
2895
2896 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTSTAT,
2897 ~(CSI_START_INTSTAT(channel->id) |
2898 CSI_DMA_END_INTSTAT(channel->id) |
2899 CSI_LINE_INTSTAT_V1(channel->id)));
2900
2901 /* enable id0 frame start int for sof(long frame, for hdr)
2902 * vehicle don't need this
2903 */
2904 if (channel->id == RKCIF_STREAM_MIPI_ID0)
2905 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTEN,
2906 CSI_START_INTEN(channel->id));
2907
2908 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
2909 0x3fff << 16 | 0x3fff);
2910 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
2911 0x3fff << 16 | 0x3fff);
2912
2913 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTEN,
2914 CSI_DMA_END_INTEN(channel->id));
2915
2916 val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) |
2917 CIF_MIPI_LVDS_SW_PRESS_ENABLE |
2918 CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(0x3) |
2919 CIF_MIPI_LVDS_SW_HURRY_ENABLE |
2920 CIF_MIPI_LVDS_SW_WATER_LINE_25 |
2921 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
2922
2923 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_CTRL, val);
2924
2925 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTEN,
2926 CSI_ALL_ERROR_INTEN_V1);
2927
2928 rkcif_write_reg(cif, get_reg_index_of_id_ctrl1(channel->id),
2929 channel->width | (channel->height << 16));
2930
2931 rkcif_write_reg(cif, get_reg_index_of_frm0_y_vlw(channel->id),
2932 channel->virtual_width);
2933
2934 if (channel->crop_en)
2935 rkcif_write_reg(cif, get_reg_index_of_id_crop_start(channel->id),
2936 channel->crop_st_y << 16 | channel->crop_st_x);
2937
2938 return 0;
2939 }
2940
vehicle_cif_stream_start(struct vehicle_cif * cif)2941 static int vehicle_cif_stream_start(struct vehicle_cif *cif)
2942 {
2943 struct vehicle_csi_channel_info *channel;
2944
2945 vehicle_cif_csi_get_vc_num(cif);
2946
2947 /* just need init virtual channel 0 */
2948 channel = &cif->channels[0];
2949 channel->id = 0;
2950 vehicle_cif_csi_channel_init(cif, channel);
2951 if (cif->chip_id < CHIP_RK3588_VEHICLE_CIF)
2952 vehicle_cif_csi_channel_set(cif, channel, V4L2_MBUS_CSI2_DPHY);
2953 else
2954 vehicle_cif_csi_channel_set_v1(cif, channel, V4L2_MBUS_CSI2_DPHY);
2955
2956 return 0;
2957 }
2958
cif_csi_stream_setup(struct vehicle_cif * cif)2959 static int cif_csi_stream_setup(struct vehicle_cif *cif)
2960 {
2961 vehicle_csi2_stream_start(cif);
2962 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588_DCPHY)
2963 vehicle_csi2_dcphy_stream_start(cif);
2964 else
2965 vehicle_csi2_dphy_stream_start(cif);
2966 vehicle_cif_stream_start(cif);
2967
2968 return 0;
2969 }
2970
vehicle_csi2_dphy_hw_do_reset(struct vehicle_cif * cif)2971 static void vehicle_csi2_dphy_hw_do_reset(struct vehicle_cif *cif)
2972 {
2973 unsigned int i;
2974 struct csi2_dphy_hw *dphy_hw = cif->dphy_hw;
2975
2976 for (i = 0; i < dphy_hw->num_dphy_rsts; i++)
2977 if (dphy_hw->dphy_rst[i])
2978 reset_control_assert(dphy_hw->dphy_rst[i]);
2979 udelay(5);
2980 for (i = 0; i < dphy_hw->num_dphy_rsts; i++)
2981 if (dphy_hw->dphy_rst[i])
2982 reset_control_deassert(dphy_hw->dphy_rst[i]);
2983 }
2984
vehicle_csi2_hw_soft_reset(struct vehicle_cif * cif)2985 static void vehicle_csi2_hw_soft_reset(struct vehicle_cif *cif)
2986 {
2987 unsigned int i;
2988 struct csi2_dphy_hw *dphy_hw = cif->dphy_hw;
2989
2990 for (i = 0; i < dphy_hw->num_csi2_rsts; i++)
2991 if (dphy_hw->csi2_rst[i])
2992 reset_control_assert(dphy_hw->csi2_rst[i]);
2993 udelay(5);
2994 for (i = 0; i < dphy_hw->num_csi2_rsts; i++)
2995 if (dphy_hw->csi2_rst[i])
2996 reset_control_deassert(dphy_hw->csi2_rst[i]);
2997 }
2998
vehicle_csi2_dphy_stream_stop(struct vehicle_cif * cif)2999 static int vehicle_csi2_dphy_stream_stop(struct vehicle_cif *cif)
3000 {
3001 struct csi2_dphy_hw *hw = cif->dphy_hw;
3002
3003 mutex_lock(&hw->mutex);
3004
3005 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
3006 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588)
3007 vehicle_csi2_dphy_hw_do_reset(cif);
3008 usleep_range(500, 1000);
3009
3010 mutex_unlock(&hw->mutex);
3011
3012 return 0;
3013 }
3014
vehicle_rkcif_disable_sys_clk(struct rk_cif_clk * clk)3015 static void vehicle_rkcif_disable_sys_clk(struct rk_cif_clk *clk)
3016 {
3017 int i;
3018
3019 for (i = clk->clks_num - 1; i >= 0; i--)
3020 clk_disable_unprepare(clk->clks[i]);
3021 }
3022
vehicle_rkcif_enable_sys_clk(struct rk_cif_clk * clk)3023 static int vehicle_rkcif_enable_sys_clk(struct rk_cif_clk *clk)
3024 {
3025 int i, ret = -EINVAL;
3026
3027 for (i = 0; i < clk->clks_num; i++) {
3028 ret = clk_prepare_enable(clk->clks[i]);
3029 if (ret < 0)
3030 goto err;
3031 }
3032
3033 return 0;
3034 err:
3035 for (--i; i >= 0; --i)
3036 clk_disable_unprepare(clk->clks[i]);
3037
3038 return ret;
3039 }
3040
3041 /* sensor mclk set */
rkcif_s_mclk(struct vehicle_cif * cif,int on,int clk_rate)3042 static void rkcif_s_mclk(struct vehicle_cif *cif, int on, int clk_rate)
3043 {
3044 int err = 0;
3045 struct device *dev = cif->dev;
3046 struct rk_cif_clk *clk = &cif->clk;
3047
3048 //return ;
3049 if (on && !clk->on) {
3050 if (!IS_ERR(clk->xvclk)) {
3051 err = clk_set_rate(clk->xvclk, clk_rate);
3052 if (err < 0)
3053 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
3054 }
3055 if (!IS_ERR(clk->xvclk)) {
3056 err = clk_prepare_enable(clk->xvclk);
3057 if (err < 0)
3058 dev_err(dev, "Failed to enable xvclk\n");
3059 }
3060 } else {
3061 if (!IS_ERR(clk->xvclk))
3062 clk_disable_unprepare(clk->xvclk);
3063 }
3064 usleep_range(2000, 5000);
3065 }
3066
rk_cif_mclk_ctrl(struct vehicle_cif * cif,int on,int clk_rate)3067 static int rk_cif_mclk_ctrl(struct vehicle_cif *cif, int on, int clk_rate)
3068 {
3069 int err = 0;
3070
3071 struct rk_cif_clk *clk = &cif->clk;
3072
3073 if (on && !clk->on) {
3074 vehicle_rkcif_enable_sys_clk(clk);
3075 clk->on = true;
3076 } else if (!on && clk->on) {
3077 vehicle_rkcif_disable_sys_clk(clk);
3078 clk->on = false;
3079 }
3080
3081 return err;
3082 }
3083
csi2_disable_dphy_clk(struct csi2_dphy_hw * hw)3084 static void csi2_disable_dphy_clk(struct csi2_dphy_hw *hw)
3085 {
3086 int i;
3087
3088 for (i = hw->num_dphy_clks - 1; i >= 0; i--) {
3089 clk_disable_unprepare(hw->dphy_clks[i].clk);
3090 VEHICLE_INFO("%s(%d) disable dphy clk: %s\n",
3091 __func__, __LINE__, hw->dphy_clks[i].id);
3092 }
3093 }
3094
csi2_enable_dphy_clk(struct csi2_dphy_hw * hw)3095 static int csi2_enable_dphy_clk(struct csi2_dphy_hw *hw)
3096 {
3097 int i, ret = -EINVAL;
3098
3099 for (i = 0; i < hw->num_dphy_clks; i++) {
3100 ret = clk_prepare_enable(hw->dphy_clks[i].clk);
3101 if (ret < 0)
3102 goto err;
3103 VEHICLE_INFO("%s(%d) enable dphy clk: %s\n",
3104 __func__, __LINE__, hw->dphy_clks[i].id);
3105 }
3106
3107 return 0;
3108 err:
3109 VEHICLE_DGERR("%s(%d) enable dphy clk: %s err\n",
3110 __func__, __LINE__, hw->dphy_clks[i].id);
3111 for (--i; i >= 0; --i)
3112 clk_disable_unprepare(hw->dphy_clks[i].clk);
3113
3114 return ret;
3115 }
3116
csi2_disable_clk(struct csi2_dphy_hw * hw)3117 static void csi2_disable_clk(struct csi2_dphy_hw *hw)
3118 {
3119 int i;
3120
3121 for (i = hw->num_csi2_clks - 1; i >= 0; i--) {
3122 clk_disable_unprepare(hw->csi2_clks[i].clk);
3123 VEHICLE_INFO("%s(%d) disable csi2 clk: %s\n",
3124 __func__, __LINE__, hw->csi2_clks[i].id);
3125 }
3126 }
3127
csi2_enable_clk(struct csi2_dphy_hw * hw)3128 static int csi2_enable_clk(struct csi2_dphy_hw *hw)
3129 {
3130 int i, ret = -EINVAL;
3131
3132 for (i = 0; i < hw->num_csi2_clks; i++) {
3133 ret = clk_prepare_enable(hw->csi2_clks[i].clk);
3134 if (ret < 0)
3135 goto err;
3136 VEHICLE_INFO("%s(%d) enable csi2 clk: %s\n",
3137 __func__, __LINE__, hw->csi2_clks[i].id);
3138 }
3139
3140 return 0;
3141 err:
3142 VEHICLE_DGERR("%s(%d) enable csi2 clk: %s err\n",
3143 __func__, __LINE__, hw->csi2_clks[i].id);
3144 for (--i; i >= 0; --i)
3145 clk_disable_unprepare(hw->csi2_clks[i].clk);
3146
3147 return ret;
3148 }
3149
vehicle_csi2_clk_ctrl(struct vehicle_cif * cif,int on)3150 static int vehicle_csi2_clk_ctrl(struct vehicle_cif *cif, int on)
3151 {
3152 int ret = 0;
3153 struct csi2_dphy_hw *dphy_hw = cif->dphy_hw;
3154
3155 on = !!on;
3156 if (on) {
3157 ret = csi2_enable_dphy_clk(dphy_hw);
3158 if (ret < 0) {
3159 VEHICLE_DGERR("enable csi dphy clk failed!");
3160 goto err;
3161 }
3162 ret = csi2_enable_clk(dphy_hw);
3163 if (ret < 0) {
3164 VEHICLE_DGERR("enable csi dphy clk failed!");
3165 goto err;
3166 }
3167 dphy_hw->on = true;
3168 } else {
3169 csi2_disable_dphy_clk(dphy_hw);
3170 csi2_disable_clk(dphy_hw);
3171 dphy_hw->on = false;
3172 }
3173
3174 return 0;
3175 err:
3176 return ret;
3177 }
3178
vehicle_csi2_stream_stop(struct vehicle_cif * cif)3179 static int vehicle_csi2_stream_stop(struct vehicle_cif *cif)
3180 {
3181 vehicle_csi2_disable(cif);
3182
3183 return 0;
3184 }
3185
vehicle_cif_stream_stop(struct vehicle_cif * cif)3186 static int vehicle_cif_stream_stop(struct vehicle_cif *cif)
3187 {
3188 return 0;
3189 }
3190
vehicle_cif_csi_stream_stop(struct vehicle_cif * cif)3191 static int vehicle_cif_csi_stream_stop(struct vehicle_cif *cif)
3192 {
3193 vehicle_cif_stream_stop(cif);
3194 vehicle_csi2_stream_stop(cif);
3195 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588_DCPHY)
3196 vehicle_csi2_dcphy_stream_stop(cif);
3197 else
3198 vehicle_csi2_dphy_stream_stop(cif);
3199
3200 return 0;
3201 }
3202
vehicle_cif_csi2_s_stream(struct vehicle_cif * cif,int enable,enum v4l2_mbus_type mbus_type)3203 static int vehicle_cif_csi2_s_stream(struct vehicle_cif *cif,
3204 int enable,
3205 enum v4l2_mbus_type mbus_type)
3206
3207 {
3208 unsigned int val = 0x0;
3209 const struct cif_input_fmt *infmt;
3210 struct vehicle_csi_channel_info *channel;
3211 int id;
3212
3213 channel = &cif->channels[0];
3214
3215 if (enable) {
3216 val = CSI_ENABLE_CAPTURE | channel->fmt_val |
3217 channel->cmd_mode_en << 4 | channel->crop_en << 5 |
3218 channel->id << 8 | channel->data_type << 10;
3219
3220 val &= ~CSI_ENABLE_MIPI_COMPACT;
3221
3222 infmt = find_input_fmt(cif->cif_cfg.mbus_code);
3223 if (!infmt) {
3224 VEHICLE_INFO("Input fmt is invalid, use default!\n");
3225 val |= CSI_YUV_INPUT_ORDER_UYVY;
3226 } else {
3227 val |= infmt->csi_yuv_order;
3228 }
3229 rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id), val);
3230 cif->state = RKCIF_STATE_STREAMING;
3231 } else {
3232 id = channel->id;
3233 val = rkcif_read_reg(cif, get_reg_index_of_id_ctrl0(id));
3234 val &= ~CSI_ENABLE_CAPTURE;
3235
3236 rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(id), val);
3237
3238 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTSTAT,
3239 CSI_START_INTSTAT(id) |
3240 CSI_DMA_END_INTSTAT(id) |
3241 CSI_LINE_INTSTAT(id));
3242
3243 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTEN,
3244 ~(CSI_START_INTEN(id) |
3245 CSI_DMA_END_INTEN(id) |
3246 CSI_LINE_INTEN(id)));
3247
3248 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTEN,
3249 ~CSI_ALL_ERROR_INTEN);
3250 cif->state = RKCIF_STATE_READY;
3251 }
3252
3253 return 0;
3254 }
3255
vehicle_cif_csi2_s_stream_v1(struct vehicle_cif * cif,int enable,enum v4l2_mbus_type mbus_type)3256 static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif,
3257 int enable,
3258 enum v4l2_mbus_type mbus_type)
3259
3260 {
3261 unsigned int val = 0x0;
3262 const struct cif_input_fmt *infmt;
3263 struct vehicle_csi_channel_info *channel;
3264 struct vehicle_cfg *cfg = &cif->cif_cfg;
3265 int id;
3266
3267 channel = &cif->channels[0];
3268
3269 if (enable) {
3270 val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE | channel->fmt_val |
3271 channel->cmd_mode_en << 26 | CSI_ENABLE_CROP_V1 |
3272 channel->id << 8 | channel->data_type << 10;
3273
3274 infmt = find_input_fmt(cif->cif_cfg.mbus_code);
3275 if (!infmt) {
3276 VEHICLE_INFO("Input fmt is invalid, use default!\n");
3277 val |= CSI_YUV_INPUT_ORDER_UYVY;
3278 } else {
3279 val |= infmt->csi_yuv_order;
3280 }
3281
3282 if (cfg->output_format == CIF_OUTPUT_FORMAT_420) {
3283 if (find_output_fmt(V4L2_PIX_FMT_NV12))
3284 val |= CSI_WRDDR_TYPE_YUV420SP_RK3588 | CSI_YUV_OUTPUT_ORDER_UYVY;
3285 } else {
3286 if (find_output_fmt(V4L2_PIX_FMT_NV16))
3287 val |= CSI_WRDDR_TYPE_YUV422SP_RK3588 | CSI_YUV_OUTPUT_ORDER_UYVY;
3288 }
3289
3290 rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id), val);
3291 rkcif_write_reg(cif, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
3292 rkcif_write_reg(cif, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
3293 cif->state = RKCIF_STATE_STREAMING;
3294 } else {
3295 id = channel->id;
3296 val = rkcif_read_reg(cif, get_reg_index_of_id_ctrl0(id));
3297 val &= ~CSI_ENABLE_CAPTURE;
3298
3299 rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(id), val);
3300
3301 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_INTSTAT,
3302 CSI_START_INTSTAT(id) |
3303 CSI_DMA_END_INTSTAT(id) |
3304 CSI_LINE_INTSTAT(id));
3305
3306 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTEN,
3307 ~(CSI_START_INTEN(id) |
3308 CSI_DMA_END_INTEN(id) |
3309 CSI_LINE_INTEN(id)));
3310
3311 rkcif_write_reg_and(cif, CIF_REG_MIPI_LVDS_INTEN,
3312 ~CSI_ALL_ERROR_INTEN);
3313 cif->state = RKCIF_STATE_READY;
3314 }
3315
3316 return 0;
3317 }
3318
cif_interrupt_setup(struct vehicle_cif * cif)3319 static int cif_interrupt_setup(struct vehicle_cif *cif)
3320 {
3321 rkcif_write_reg(cif, CIF_REG_DVP_INTEN,
3322 FRAME_END_EN | INTSTAT_ERR |
3323 PST_INF_FRAME_END);
3324
3325 /* enable line int for sof */
3326 rkcif_write_reg(cif, CIF_REG_DVP_LINE_INT_NUM, 0x1);
3327 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, LINE_INT_EN);
3328
3329 return 0;
3330 }
3331
vehicle_cif_dvp_dump_regs(struct vehicle_cif * cif)3332 static void vehicle_cif_dvp_dump_regs(struct vehicle_cif *cif)
3333 {
3334 int val;
3335
3336 if (!vehicle_debug)
3337 return;
3338
3339 val = rkcif_read_reg(cif, CIF_REG_DVP_CTRL);
3340 VEHICLE_DG("CIF_REG_DVP_CTRL = 0x%x\r\n", val);
3341
3342 val = rkcif_read_reg(cif, CIF_REG_DVP_INTEN);
3343 VEHICLE_DG("CIF_REG_DVP_INTEN = 0x%x\r\n", val);
3344
3345 val = rkcif_read_reg(cif, CIF_REG_DVP_INTSTAT);
3346 VEHICLE_DG("CIF_REG_DVP_INTSTAT = 0x%x\r\n", val);
3347
3348 val = rkcif_read_reg(cif, CIF_REG_DVP_FOR);
3349 VEHICLE_DG("CIF_REG_DVP_FOR = 0x%x\r\n", val);
3350
3351 val = rkcif_read_reg(cif, CIF_REG_DVP_MULTI_ID);
3352 VEHICLE_DG("CIF_REG_DVP_MULTI_ID = 0x%x\r\n", val);
3353
3354 val = rkcif_read_reg(cif, CIF_REG_DVP_LINE_NUM_ADDR);
3355 VEHICLE_DG("CIF_REG_DVP_LINE_NUM_ADDR = 0X%x\r\n", val);
3356
3357 val = rkcif_read_reg(cif, CIF_REG_DVP_FRM0_ADDR_Y);
3358 VEHICLE_DG("CIF_REG_DVP_FRM0_ADDR_Y = 0X%x\r\n", val);
3359
3360 val = rkcif_read_reg(cif, CIF_REG_DVP_FRM0_ADDR_UV);
3361 VEHICLE_DG("CIF_REG_DVP_FRM0_ADDR_UV = 0X%x\r\n", val);
3362
3363 val = rkcif_read_reg(cif, CIF_REG_DVP_FRM1_ADDR_Y);
3364 VEHICLE_DG("CIF_REG_DVP_FRM1_ADDR_Y = 0X%x\r\n", val);
3365
3366 val = rkcif_read_reg(cif, CIF_REG_DVP_FRM1_ADDR_UV);
3367 VEHICLE_DG("CIF_REG_DVP_FRM1_ADDR_UV = 0X%x\r\n", val);
3368
3369 val = rkcif_read_reg(cif, CIF_REG_DVP_VIR_LINE_WIDTH);
3370 VEHICLE_DG("CIF_REG_DVP_VIR_LINE_WIDTH = 0X%x\r\n", val);
3371
3372 val = rkcif_read_reg(cif, CIF_REG_DVP_SET_SIZE);
3373 VEHICLE_DG("CIF_REG_DVP_SET_SIZE = 0x%x\r\n", val);
3374
3375 val = rkcif_read_reg(cif, CIF_REG_DVP_LINE_INT_NUM);
3376 VEHICLE_DG("CIF_REG_DVP_LINE_INT_NUM = 0x%x\r\n", val);
3377
3378 val = rkcif_read_reg(cif, CIF_REG_DVP_LINE_CNT);
3379 VEHICLE_DG("CIF_REG_DVP_LINE_CNT = 0x%x\r\n", val);
3380
3381 val = rkcif_read_reg(cif, CIF_REG_DVP_CROP);
3382 VEHICLE_DG("CIF_REG_DVP_CROP = 0x%x\r\n", val);
3383
3384 val = rkcif_read_reg(cif, CIF_REG_DVP_SCL_CTRL);
3385 VEHICLE_DG("CIF_REG_DVP_SCL_CTRL = 0x%x\r\n", val);
3386
3387 val = rkcif_read_reg(cif, CIF_REG_DVP_FRAME_STATUS);
3388 VEHICLE_DG("CIF_REG_DVP_FRAME_STATUS = 0X%x\r\n", val);
3389
3390 val = rkcif_read_reg(cif, CIF_REG_DVP_CUR_DST);
3391 VEHICLE_DG("CIF_REG_DVP_CUR_DST = 0X%x\r\n", val);
3392
3393 val = rkcif_read_reg(cif, CIF_REG_DVP_LAST_LINE);
3394 VEHICLE_DG("CIF_REG_DVP_LAST_LINE = 0X%x\r\n", val);
3395
3396 val = rkcif_read_reg(cif, CIF_REG_DVP_LAST_PIX);
3397 VEHICLE_DG("CIF_REG_DVP_LAST_PIX = 0X%x\r\n", val);
3398
3399 val = rkcif_read_reg(cif, CIF_REG_DVP_SCL_VALID_NUM);
3400 VEHICLE_DG("CIF_REG_DVP_SCL_VALID_NUM = 0X%x\r\n", val);
3401
3402 val = rkcif_read_reg(cif, CIF_REG_DVP_LINE_NUM_ADDR);
3403 VEHICLE_DG("CIF_REG_DVP_LINE_NUM_ADDR = 0X%x\r\n", val);
3404
3405 /* read dvp clk sample edge */
3406 val = rkvehicle_cif_read_grf_reg(cif, CIF_REG_GRF_CIFIO_CON);
3407 VEHICLE_DG("CIF_REG_GRF_CIFIO_CON = 0X%x\r\n", val);
3408 }
3409
vehicle_cif_csi2_dump_regs(struct vehicle_cif * cif)3410 static void vehicle_cif_csi2_dump_regs(struct vehicle_cif *cif)
3411 {
3412 int val = 0;
3413 void __iomem *csi2_base = cif->csi2_base;
3414 struct csi2_dphy_hw *hw = cif->dphy_hw;
3415
3416 if (!vehicle_debug)
3417 return;
3418
3419 /* 1. dump csi2-dphy regs */
3420 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588) {
3421 VEHICLE_DG("\n\n DUMP CSI-DPHY REGS: \r\n");
3422 read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &val);
3423 VEHICLE_DG("CSI2PHY_REG_CTRL_LANE_ENABLE = 0x%x\r\n", val);
3424
3425 read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
3426 VEHICLE_DG("CSI2PHY_DUAL_CLK_EN = 0x%x\r\n", val);
3427
3428 val = csi2_dphy_read_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE);
3429 VEHICLE_DG("GRF_DPHY_CSI2PHY_FORCERXMODE = 0x%x\r\n", val);
3430
3431 val = csi2_dphy_read_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL);
3432 VEHICLE_DG("GRF_DPHY_CSI2PHY_LANE_SEL = 0x%x\r\n", val);
3433
3434 val = csi2_dphy_read_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN);
3435 VEHICLE_DG("GRF_DPHY_CSI2PHY_DATALANE_EN = 0x%x\r\n", val);
3436
3437 val = csi2_dphy_read_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN);
3438 VEHICLE_DG("GRF_DPHY_CSI2PHY_CLKLANE_EN = 0x%x\r\n", val);
3439 }
3440
3441 /* 2. dump csi2 regs */
3442 VEHICLE_DG("\n\n DUMP CSI2 REGS: \r\n");
3443 val = vehicle_read_csihost_reg(csi2_base, CSIHOST_N_LANES);
3444 VEHICLE_DG("CSIHOST_N_LANES = 0x%x\r\n", val);
3445
3446 val = vehicle_read_csihost_reg(csi2_base, CSIHOST_CONTROL);
3447 VEHICLE_DG("CSIHOST_CONTROL = 0x%x\r\n", val);
3448
3449 val = vehicle_read_csihost_reg(csi2_base, CSIHOST_MSK1);
3450 VEHICLE_DG("CSIHOST_MSK1 = 0x%x\r\n", val);
3451
3452 val = vehicle_read_csihost_reg(csi2_base, CSIHOST_MSK2);
3453 VEHICLE_DG("CSIHOST_MSK2 = 0x%x\r\n", val);
3454
3455 val = vehicle_read_csihost_reg(csi2_base, CSIHOST_RESETN);
3456 VEHICLE_DG("CSIHOST_RESETN = 0x%x\r\n", val);
3457
3458 /* 3. dump cif regs */
3459 VEHICLE_DG("\n\n DUMP MIPI CIF REGS: \r\n");
3460 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_CTRL);
3461 VEHICLE_DG("CIF_REG_MIPI_LVDS_CTRL = 0x%x\r\n", val);
3462
3463 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_INTEN);
3464 VEHICLE_DG("CIF_REG_MIPI_LVDS_INTEN = 0x%x\r\n", val);
3465
3466 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_INTSTAT);
3467 VEHICLE_DG("CIF_REG_MIPI_LVDS_INTSTAT = 0x%x\r\n", val);
3468
3469 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_ID0_CTRL0);
3470 VEHICLE_DG("CIF_REG_MIPI_LVDS_ID0_CTRL0 = 0x%x\r\n", val);
3471
3472 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_ID0_CTRL1);
3473 VEHICLE_DG("CIF_REG_MIPI_LVDS_ID0_CTRL1 = 0x%x\r\n", val);
3474
3475 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1);
3476 VEHICLE_DG("CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1 = 0x%x\r\n", val);
3477
3478 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3);
3479 VEHICLE_DG("CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3 = 0x%x\r\n", val);
3480
3481 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0);
3482 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0 = 0X%x\r\n", val);
3483
3484 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0);
3485 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0 = 0X%x\r\n", val);
3486
3487 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0);
3488 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0 = 0X%x\r\n", val);
3489
3490 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0);
3491 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0 = 0X%x\r\n", val);
3492
3493 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0);
3494 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0 = 0X%x\r\n", val);
3495
3496 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0);
3497 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0 = 0X%x\r\n", val);
3498
3499 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0);
3500 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0 = 0X%x\r\n", val);
3501
3502 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0);
3503 VEHICLE_DG("CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0 = 0X%x\r\n", val);
3504
3505 val = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_ID0_CROP_START);
3506 VEHICLE_DG("CIF_REG_MIPI_LVDS_ID0_CROP_START = 0X%x\r\n", val);
3507
3508 /* read dvp clk sample edge */
3509 val = rkvehicle_cif_read_grf_reg(cif, CIF_REG_GRF_CIFIO_CON);
3510 VEHICLE_DG("CIF_REG_GRF_CIFIO_CON = 0X%x\r\n", val);
3511 }
3512
vehicle_cif_s_stream(struct vehicle_cif * cif,int enable)3513 static int vehicle_cif_s_stream(struct vehicle_cif *cif, int enable)
3514 {
3515 int cif_ctrl_val;
3516 unsigned int dma_en = 0;
3517
3518 cif->is_enabled = enable;
3519
3520 VEHICLE_INFO("%s enable=%d\n", __func__, enable);
3521
3522 if (enable) {
3523 cif->irqinfo.cifirq_idx = 0;
3524 cif->irqinfo.cifirq_normal_idx = 0;
3525 cif->irqinfo.cifirq_abnormal_idx = 0;
3526 cif->irqinfo.dmairq_idx = 0;
3527 cif->irqinfo.all_err_cnt = 0;
3528 cif->irqinfo.dvp_bus_err_cnt = 0;
3529 cif->irqinfo.dvp_overflow_cnt = 0;
3530 cif->irqinfo.dvp_pix_err_cnt = 0;
3531 cif->irqinfo.dvp_line_err_cnt = 0;
3532 cif->irqinfo.dvp_size_err_cnt = 0;
3533 cif->irqinfo.dvp_bwidth_lack_cnt = 0;
3534 cif->irqinfo.csi_size_err_cnt = 0;
3535
3536 rkcif_write_reg(cif, CIF_REG_DVP_INTEN,
3537 FRAME_END_EN | INTSTAT_ERR |
3538 PST_INF_FRAME_END);
3539
3540 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
3541 rkcif_write_reg(cif, CIF_REG_DVP_LINE_INT_NUM, 0x1);
3542 rkcif_write_reg_or(cif, CIF_REG_DVP_INTEN, 0x033ffff);
3543 }
3544
3545 dma_en = DVP_DMA_EN;
3546 if (cif->chip_id < CHIP_RK3588_VEHICLE_CIF)
3547 rkcif_write_reg(cif, CIF_REG_DVP_CTRL,
3548 AXI_BURST_16 | MODE_PINGPONG | ENABLE_CAPTURE);
3549 else
3550 rkcif_write_reg(cif, CIF_REG_DVP_CTRL,
3551 DVP_SW_WATER_LINE_25
3552 | dma_en
3553 | DVP_PRESS_EN
3554 | DVP_HURRY_EN
3555 | DVP_SW_WATER_LINE_25
3556 | DVP_SW_PRESS_VALUE(3)
3557 | DVP_SW_HURRY_VALUE(3)
3558 | ENABLE_CAPTURE);
3559 cif->frame_idx = 0;
3560 cif->state = RKCIF_STATE_STREAMING;
3561 } else {
3562 cif_ctrl_val = rkcif_read_reg(cif, CIF_REG_DVP_CTRL);
3563 cif_ctrl_val &= ~ENABLE_CAPTURE;
3564 rkcif_write_reg(cif, CIF_REG_DVP_CTRL, cif_ctrl_val);
3565 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, 0);
3566 rkcif_write_reg(cif, CIF_REG_DVP_INTSTAT, 0x3ff);
3567 rkcif_write_reg(cif, CIF_REG_DVP_FRAME_STATUS, 0x0);
3568 cif->state = RKCIF_STATE_READY;
3569 }
3570
3571 return 0;
3572 }
3573
vehicle_cif_create_dummy_buf(struct vehicle_cif * cif)3574 static int vehicle_cif_create_dummy_buf(struct vehicle_cif *cif)
3575 {
3576 struct vehicle_rkcif_dummy_buffer *dummy_buf = &cif->dummy_buf;
3577 struct vehicle_cfg *cfg = &cif->cif_cfg;
3578
3579 /* get a maximum plane size */
3580 dummy_buf->size = cfg->width * cfg->height * 2;
3581
3582 dummy_buf->vaddr = dma_alloc_coherent(cif->dev, dummy_buf->size,
3583 &dummy_buf->dma_addr,
3584 GFP_KERNEL);
3585 if (!dummy_buf->vaddr) {
3586 VEHICLE_DGERR("Failed to allocate the memory for dummy buffer\n");
3587 return -ENOMEM;
3588 }
3589
3590 VEHICLE_INFO("Allocate dummy buffer, size: 0x%08x\n", dummy_buf->size);
3591
3592 return 0;
3593 }
3594
vehicle_cif_destroy_dummy_buf(struct vehicle_cif * cif)3595 static void vehicle_cif_destroy_dummy_buf(struct vehicle_cif *cif)
3596 {
3597 struct vehicle_rkcif_dummy_buffer *dummy_buf = &cif->dummy_buf;
3598
3599 VEHICLE_INFO("Destroy dummy buffer, size: 0x%08x\n", dummy_buf->size);
3600
3601 if (dummy_buf->vaddr)
3602 dma_free_coherent(cif->dev, dummy_buf->size,
3603 dummy_buf->vaddr, dummy_buf->dma_addr);
3604 dummy_buf->dma_addr = 0;
3605 dummy_buf->vaddr = NULL;
3606 }
3607
vehicle_cif_hw_soft_reset(struct vehicle_cif * cif)3608 static void vehicle_cif_hw_soft_reset(struct vehicle_cif *cif)
3609 {
3610 unsigned int i;
3611 struct rk_cif_clk *clk = &cif->clk;
3612
3613 for (i = 0; i < clk->rsts_num; i++)
3614 if (clk->cif_rst[i])
3615 reset_control_assert(clk->cif_rst[i]);
3616 udelay(10);
3617 for (i = 0; i < clk->rsts_num; i++)
3618 if (clk->cif_rst[i])
3619 reset_control_deassert(clk->cif_rst[i]);
3620 }
3621
vehicle_rkcif_do_soft_reset(struct vehicle_cif * cif)3622 static void vehicle_rkcif_do_soft_reset(struct vehicle_cif *cif)
3623 {
3624 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY)
3625 rkcif_write_reg_or(cif, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
3626 else
3627 rkcif_write_reg_or(cif, CIF_REG_DVP_CTRL, 0x000A0000);
3628 usleep_range(10, 20);
3629 VEHICLE_INFO("vicap do soft reset 0x%x\n", 0x000A0000);
3630 }
3631
vehicle_cif_do_stop_stream(struct vehicle_cif * cif)3632 static int vehicle_cif_do_stop_stream(struct vehicle_cif *cif)
3633 {
3634 if (!cif)
3635 return -1;
3636
3637 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
3638 if (cif->chip_id >= CHIP_RK3588_VEHICLE_CIF) {
3639 vehicle_cif_csi2_s_stream_v1(cif, 0, V4L2_MBUS_CSI2_DPHY);
3640 vehicle_cif_csi_stream_stop(cif);
3641 } else {
3642 vehicle_cif_csi2_s_stream(cif, 0, V4L2_MBUS_CSI2_DPHY);
3643 vehicle_cif_csi_stream_stop(cif);
3644 }
3645 } else {
3646 vehicle_cif_s_stream(cif, 0);
3647 }
3648 if (cif->chip_id >= CHIP_RK3588_VEHICLE_CIF)
3649 vehicle_rkcif_do_soft_reset(cif);
3650 vehicle_cif_destroy_dummy_buf(cif);
3651
3652 return 0;
3653 }
3654
vehicle_cif_do_start_stream(struct vehicle_cif * cif)3655 static int vehicle_cif_do_start_stream(struct vehicle_cif *cif)
3656 {
3657 int ret = 0;
3658
3659 if (!cif)
3660 return -ENODEV;
3661
3662 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
3663
3664 /* 1. stream setup */
3665 cif_csi_stream_setup(cif);
3666
3667 /* 2. create dummy buf */
3668 ret = vehicle_cif_create_dummy_buf(cif);
3669 if (ret < 0)
3670 VEHICLE_DGERR("Failed to create dummy_buf, %d\n", ret);
3671
3672 /* 3. cif init buffer */
3673 if (vehicle_cif_init_buffer(cif, 1, cif->channels[0].id) < 0)
3674 return -EINVAL;
3675
3676 /* 4. dump cif regs */
3677 vehicle_cif_csi2_dump_regs(cif);
3678
3679 /* 5. start stream */
3680 if (cif->chip_id >= CHIP_RK3588_VEHICLE_CIF)
3681 vehicle_cif_csi2_s_stream_v1(cif, 1, V4L2_MBUS_CSI2_DPHY);
3682 else
3683 vehicle_cif_csi2_s_stream(cif, 1, V4L2_MBUS_CSI2_DPHY);
3684
3685 } else {
3686 /* 1. stream setup */
3687 cif_stream_setup(cif);
3688
3689 /* 2. create dummy buf */
3690 ret = vehicle_cif_create_dummy_buf(cif);
3691 if (ret < 0)
3692 VEHICLE_DGERR("Failed to create dummy_buf, %d\n", ret);
3693
3694 /* 3. cif init buffer */
3695 if (vehicle_cif_init_buffer(cif, 1, 0) < 0)
3696 return -EINVAL;
3697
3698 /* 4. enable interrupts */
3699 if (cif->chip_id < CHIP_RK3588_VEHICLE_CIF)
3700 cif_interrupt_setup(cif);
3701
3702 /* 5. dump cif regs */
3703 vehicle_cif_dvp_dump_regs(cif);
3704
3705 /* 6. start stream */
3706 vehicle_cif_s_stream(cif, 1);
3707 }
3708
3709 return 0;
3710 }
3711
3712 static void vehicle_rkcif_disable_sys_clk(struct rk_cif_clk *clk);
3713 static int vehicle_rkcif_enable_sys_clk(struct rk_cif_clk *clk);
3714
vehicle_cif_reset(struct vehicle_cif * cif,int only_rst)3715 static void vehicle_cif_reset(struct vehicle_cif *cif, int only_rst)
3716 {
3717 int ret = 0;
3718
3719 mutex_lock(&cif->stream_lock);
3720 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
3721 VEHICLE_DG("%s enter, V4L2_MBUS_CSI2 reset need to do!\n", __func__);
3722
3723 // goto unlock_reset;
3724 if (only_rst == 1) {
3725 vehicle_cif_hw_soft_reset(cif);
3726 } else {
3727 vehicle_cif_do_stop_stream(cif);
3728 vehicle_cif_hw_soft_reset(cif);
3729 vehicle_cif_do_start_stream(cif);
3730 }
3731 } else {
3732 int ctrl_reg, inten_reg, crop_reg, set_size_reg, for_reg;
3733 int vir_line_width_reg, scl_reg;
3734 int y0_reg, uv0_reg, y1_reg, uv1_reg;
3735
3736 VEHICLE_DG("%s enter, do reset!\n", __func__);
3737 if (only_rst == 1) {
3738 vehicle_cif_hw_soft_reset(cif);
3739 } else {
3740 ctrl_reg = rkcif_read_reg(cif, CIF_REG_DVP_CTRL);
3741 if (ctrl_reg & ENABLE_CAPTURE)
3742 rkcif_write_reg(cif, CIF_REG_DVP_CTRL,
3743 ctrl_reg & ~ENABLE_CAPTURE);
3744
3745 crop_reg = rkcif_read_reg(cif, CIF_REG_DVP_CROP);
3746 set_size_reg = rkcif_read_reg(cif, CIF_REG_DVP_SET_SIZE);
3747 inten_reg = rkcif_read_reg(cif, CIF_REG_DVP_INTEN);
3748 for_reg = rkcif_read_reg(cif, CIF_REG_DVP_FOR);
3749 vir_line_width_reg = rkcif_read_reg(cif,
3750 CIF_REG_DVP_VIR_LINE_WIDTH);
3751 scl_reg = rkcif_read_reg(cif, CIF_REG_DVP_SCL_CTRL);
3752 y0_reg = rkcif_read_reg(cif, CIF_REG_DVP_FRM0_ADDR_Y);
3753 uv0_reg = rkcif_read_reg(cif, CIF_REG_DVP_FRM0_ADDR_UV);
3754 y1_reg = rkcif_read_reg(cif, CIF_REG_DVP_FRM1_ADDR_Y);
3755 uv1_reg = rkcif_read_reg(cif, CIF_REG_DVP_FRM1_ADDR_UV);
3756
3757 udelay(20);
3758 vehicle_cif_hw_soft_reset(cif);
3759 vehicle_rkcif_disable_sys_clk(&cif->clk);
3760 udelay(5);
3761 ret = vehicle_rkcif_enable_sys_clk(&cif->clk);
3762 if (ret < 0) {
3763 VEHICLE_DGERR("@%s, resume cif clk failed!\n", __func__);
3764 goto unlock_reset;
3765 }
3766
3767 rkcif_write_reg(cif, CIF_REG_DVP_CTRL,
3768 ctrl_reg & ~ENABLE_CAPTURE);
3769 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, inten_reg);
3770 rkcif_write_reg(cif, CIF_REG_DVP_CROP, crop_reg);
3771 rkcif_write_reg(cif, CIF_REG_DVP_SET_SIZE, set_size_reg);
3772 rkcif_write_reg(cif, CIF_REG_DVP_FOR, for_reg);
3773 rkcif_write_reg(cif, CIF_REG_DVP_VIR_LINE_WIDTH,
3774 vir_line_width_reg);
3775 rkcif_write_reg(cif, CIF_REG_DVP_SCL_CTRL, scl_reg);
3776 rkcif_write_reg(cif, CIF_REG_DVP_FRM0_ADDR_Y, y0_reg);
3777 rkcif_write_reg(cif, CIF_REG_DVP_FRM0_ADDR_UV, uv0_reg);
3778 rkcif_write_reg(cif, CIF_REG_DVP_FRM1_ADDR_Y, y1_reg);
3779 rkcif_write_reg(cif, CIF_REG_DVP_FRM1_ADDR_UV, uv1_reg);
3780 }
3781 }
3782 unlock_reset:
3783 mutex_unlock(&cif->stream_lock);
3784 }
3785
vehicle_cif_reset_delay(struct vehicle_cif * cif)3786 static void vehicle_cif_reset_delay(struct vehicle_cif *cif)
3787 {
3788 mdelay(10);
3789 vehicle_cif_reset(cif, 0);
3790 mdelay(10);
3791 vehicle_cif_s_stream(cif, 1);
3792 }
3793
cif_capture_en(char * reg,int enable)3794 static void cif_capture_en(char *reg, int enable)
3795 {
3796 int val = 0;
3797
3798 val = read_reg(reg, CIF_REG_DVP_CTRL);
3799 if (enable == 1)
3800 write_reg(reg, CIF_REG_DVP_CTRL, val | ENABLE_CAPTURE);
3801 else
3802 write_reg(reg, CIF_REG_DVP_CTRL, val & (~ENABLE_CAPTURE));
3803 }
3804
vehicle_cif_reset_work_func(struct work_struct * work)3805 static void vehicle_cif_reset_work_func(struct work_struct *work)
3806 {
3807 struct vehicle_cif *cif = container_of(work, struct vehicle_cif,
3808 work.work);
3809
3810 if (cif->stopping)
3811 return;
3812
3813 atomic_set(&cif->reset_status, 1);
3814 vehicle_cif_reset_delay(cif);
3815 atomic_set(&cif->reset_status, 0);
3816 wake_up(&cif->wq_stopped);
3817 }
3818
vehicle_wait_cif_reset_done(void)3819 int vehicle_wait_cif_reset_done(void)
3820 {
3821 struct vehicle_cif *cif = g_cif;
3822 int ret = 0, retry = 2;
3823
3824 for (retry = 2; retry >= 0; retry--) {
3825 ret = wait_event_timeout(cif->wq_stopped,
3826 !atomic_read(&cif->reset_status),
3827 msecs_to_jiffies(200));
3828 if (!ret) {
3829 VEHICLE_DG("%s wait cif reset timeout, left try times(%d)!\n",
3830 __func__, retry);
3831 } else {
3832 break;
3833 }
3834 }
3835
3836 return 0;
3837 }
3838
cif_irq_error_process(struct vehicle_cif * cif,unsigned int reg_intstat)3839 static int cif_irq_error_process(struct vehicle_cif *cif, unsigned int reg_intstat)
3840 {
3841 VEHICLE_DG("%s cif->irqinfo.all_err_cnt(%lld)\n", __func__,
3842 cif->irqinfo.all_err_cnt);
3843 if (reg_intstat & INTSTAT_ERR) {
3844 cif->irqinfo.all_err_cnt++;
3845
3846 if (reg_intstat & BUS_ERR) {
3847 cif->irqinfo.dvp_bus_err_cnt++;
3848 VEHICLE_DGERR("dvp bus err\n");
3849 }
3850
3851 if (reg_intstat & DVP_ALL_OVERFLOW) {
3852 cif->irqinfo.dvp_overflow_cnt++;
3853 VEHICLE_DGERR("dvp overflow err\n");
3854 }
3855
3856 if (reg_intstat & LINE_ERR) {
3857 cif->irqinfo.dvp_line_err_cnt++;
3858 VEHICLE_DGERR("dvp line err\n");
3859 }
3860
3861 if (reg_intstat & PIX_ERR) {
3862 cif->irqinfo.dvp_pix_err_cnt++;
3863 VEHICLE_DGERR("dvp pix err\n");
3864 }
3865
3866 if (cif->irqinfo.all_err_cnt < 10) {
3867 u32 mask;
3868
3869 VEHICLE_DGERR("ERROR: DVP_ALL_ERROR:0x%x!!\n", reg_intstat);
3870 mask = rkcif_read_reg(cif, CIF_REG_DVP_INTEN);
3871 mask &= ~INTSTAT_ERR;
3872 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, mask);
3873 return -2;
3874 } else if (cif->irqinfo.all_err_cnt >= 10) {
3875 u32 mask;
3876
3877 mask = rkcif_read_reg(cif, CIF_REG_DVP_INTEN);
3878 mask &= ~INTSTAT_ERR;
3879 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, mask);
3880 VEHICLE_DGERR("ERROR: DVP_ALL_ERROR:0x%x!!\n", reg_intstat);
3881 return -2;
3882 }
3883 }
3884
3885 return 0;
3886 }
3887
vehicle_cif_csi2_g_mipi_id(unsigned int intstat)3888 static int vehicle_cif_csi2_g_mipi_id(unsigned int intstat)
3889 {
3890 if (intstat & CSI_FRAME_END_ID0) {
3891 if ((intstat & CSI_FRAME_END_ID0) == CSI_FRAME_END_ID0)
3892 VEHICLE_DG("frame0/1 trigger simultaneously in ID0\n");
3893 return RKCIF_STREAM_MIPI_ID0;
3894 }
3895
3896 if (intstat & CSI_FRAME_END_ID1) {
3897 if ((intstat & CSI_FRAME_END_ID1) == CSI_FRAME_END_ID1)
3898 VEHICLE_DG("frame0/1 trigger simultaneously in ID1\n");
3899 return RKCIF_STREAM_MIPI_ID1;
3900 }
3901
3902 if (intstat & CSI_FRAME_END_ID2) {
3903 if ((intstat & CSI_FRAME_END_ID2) == CSI_FRAME_END_ID2)
3904 VEHICLE_DG("frame0/1 trigger simultaneously in ID2\n");
3905 return RKCIF_STREAM_MIPI_ID2;
3906 }
3907
3908 if (intstat & CSI_FRAME_END_ID3) {
3909 if ((intstat & CSI_FRAME_END_ID3) == CSI_FRAME_END_ID3)
3910 VEHICLE_DG("frame0/1 trigger simultaneously in ID3\n");
3911 return RKCIF_STREAM_MIPI_ID3;
3912 }
3913
3914 return -EINVAL;
3915 }
3916
rkcif_dvp_g_ch_id_by_fe(unsigned int intstat)3917 static __maybe_unused int rkcif_dvp_g_ch_id_by_fe(unsigned int intstat)
3918 {
3919 if (intstat & DVP_ALL_END_ID0) {
3920 if ((intstat & DVP_ALL_END_ID0) ==
3921 DVP_ALL_END_ID0)
3922 VEHICLE_DG("frame0/1 trigger simultaneously in DVP ID0\n");
3923 return RKCIF_STREAM_MIPI_ID0;
3924 }
3925
3926 if (intstat & DVP_ALL_END_ID1) {
3927 if ((intstat & DVP_ALL_END_ID1) ==
3928 DVP_ALL_END_ID1)
3929 VEHICLE_DG("frame0/1 trigger simultaneously in DVP ID1\n");
3930 return RKCIF_STREAM_MIPI_ID1;
3931 }
3932
3933 if (intstat & DVP_ALL_END_ID2) {
3934 if ((intstat & DVP_ALL_END_ID2) ==
3935 DVP_ALL_END_ID2)
3936 VEHICLE_DG("frame0/1 trigger simultaneously in DVP ID2\n");
3937 return RKCIF_STREAM_MIPI_ID2;
3938 }
3939
3940 if (intstat & DVP_ALL_END_ID3) {
3941 if ((intstat & DVP_ALL_END_ID3) ==
3942 DVP_ALL_END_ID3)
3943 VEHICLE_DG("frame0/1 trigger simultaneously in DVP ID3\n");
3944 return RKCIF_STREAM_MIPI_ID3;
3945 }
3946
3947 return -EINVAL;
3948 }
3949
vehicle_cif_next_buffer(struct vehicle_cif * cif,u32 frame_ready,int mipi_id)3950 static int vehicle_cif_next_buffer(struct vehicle_cif *cif, u32 frame_ready, int mipi_id)
3951 {
3952 u32 frm0_addr_y, frm0_addr_uv;
3953 u32 frm1_addr_y, frm1_addr_uv;
3954 unsigned long y_addr = 0, uv_addr = 0;
3955 static unsigned long temp_y_addr, temp_uv_addr;
3956 int commit_buf = 0;
3957 struct vehicle_rkcif_dummy_buffer *dummy_buf = &cif->dummy_buf;
3958 u32 frm_num_reg, frame_id = 0;
3959 VEHICLE_DG("@%s, enter, mipi_id(%d)\n", __func__, mipi_id);
3960
3961 if ((frame_ready > 1) || (cif->cif_cfg.buf_num < 2) ||
3962 (cif->cif_cfg.buf_num > MAX_BUF_NUM))
3963 return 0;
3964
3965 cif->last_buf_index = cif->current_buf_index;
3966 cif->current_buf_index = (cif->current_buf_index + 1) %
3967 cif->cif_cfg.buf_num;
3968
3969 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
3970 frm0_addr_y = get_reg_index_of_frm0_y_addr(mipi_id);
3971 frm0_addr_uv = get_reg_index_of_frm0_uv_addr(mipi_id);
3972 frm1_addr_y = get_reg_index_of_frm1_y_addr(mipi_id);
3973 frm1_addr_uv = get_reg_index_of_frm1_uv_addr(mipi_id);
3974 frm_num_reg = get_reg_index_of_frm_num(mipi_id);
3975 frame_id = rkcif_read_reg(cif, frm_num_reg);
3976 VEHICLE_DG("@%s, frm_num_reg(0x%x), frame_id:0x%x\n", __func__,
3977 frm_num_reg, frame_id);
3978 } else {
3979 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(mipi_id);
3980 frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(mipi_id);
3981 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(mipi_id);
3982 frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(mipi_id);
3983 }
3984
3985 spin_lock(&cif->vbq_lock);
3986
3987 if (!cif->interlaced_enable) {
3988 temp_y_addr = vehicle_flinger_request_cif_buffer();
3989 if (temp_y_addr == 0) {
3990 VEHICLE_INFO("%s,warnning request buffer failed\n", __func__);
3991 spin_unlock(&cif->vbq_lock);
3992 if (dummy_buf->vaddr) {
3993 if (frame_ready == 0) {
3994 rkcif_write_reg(cif, frm0_addr_y, dummy_buf->dma_addr);
3995 rkcif_write_reg(cif, frm0_addr_uv, dummy_buf->dma_addr);
3996 } else {
3997 rkcif_write_reg(cif, frm1_addr_y, dummy_buf->dma_addr);
3998 rkcif_write_reg(cif, frm1_addr_uv, dummy_buf->dma_addr);
3999 }
4000 VEHICLE_INFO("frame Drop to dummy buf\n");
4001 } else {
4002 VEHICLE_INFO("dummy buf is null!\n");
4003 }
4004 return -1;
4005 }
4006 temp_uv_addr = temp_y_addr + UV_OFFSET;
4007 y_addr = temp_y_addr;
4008 uv_addr = temp_uv_addr;
4009 commit_buf = 0;
4010 } else {
4011 if ((frame_id != 0 && (frame_id & 0xffff) % 2 == 0) ||
4012 (frame_id == 0 && (cif->interlaced_counts % 2 == 0))) {
4013 temp_y_addr = vehicle_flinger_request_cif_buffer();
4014 if (temp_y_addr == 0) {
4015 VEHICLE_DGERR("%s,warnning request buffer failed\n", __func__);
4016 spin_unlock(&cif->vbq_lock);
4017 return -1;
4018 }
4019 temp_uv_addr = temp_y_addr + UV_OFFSET;
4020 y_addr = temp_y_addr;
4021 uv_addr = temp_uv_addr;
4022 commit_buf = -1; //not ok yet
4023 } else {
4024 y_addr = temp_y_addr + cif->interlaced_offset;
4025 //uv_addr = temp_uv_addr;
4026 uv_addr = temp_uv_addr + cif->interlaced_offset;
4027 commit_buf = 0; //even & odd field add
4028 if (temp_y_addr == 0) {
4029 VEHICLE_DGERR("%s,warnning temp_y_addr is NULL!\n", __func__);
4030 spin_unlock(&cif->vbq_lock);
4031 return -1;
4032 }
4033 }
4034 WARN_ON(y_addr == cif->interlaced_offset);
4035 WARN_ON(uv_addr == cif->interlaced_offset);
4036 }
4037
4038 if (frame_ready == 0) {
4039 rkcif_write_reg(cif, frm0_addr_y, y_addr);
4040 rkcif_write_reg(cif, frm0_addr_uv, uv_addr);
4041 cif->active[0] = temp_y_addr;
4042 } else {
4043 rkcif_write_reg(cif, frm1_addr_y, y_addr);
4044 rkcif_write_reg(cif, frm1_addr_uv, uv_addr);
4045 cif->active[1] = temp_y_addr;
4046 }
4047 cif->interlaced_counts++;
4048 spin_unlock(&cif->vbq_lock);
4049
4050 return commit_buf;
4051 }
4052
4053 /***************************** irq operation ******************************/
4054 //discard the first few frames to solve display abnormality after different model camera switch
4055 static int drop_frames_number;
rk_camera_irq(int irq,void * data)4056 static irqreturn_t rk_camera_irq(int irq, void *data)
4057 {
4058 struct vehicle_cif *cif = (struct vehicle_cif *)data;
4059 u32 lastline, lastpix, ctl;
4060 u32 cif_frmst, frmid, int_en;
4061 unsigned int intstat, i = 0xff;
4062 int frame_ready = 0;
4063 int frame_phase = 0;
4064 unsigned long addr;
4065 int mipi_id = 0;
4066
4067 if (drop_frames_number > 0) {
4068 VEHICLE_INFO("%s discard the first few frames!\n", __func__);
4069 drop_frames_number--;
4070 goto IRQ_EXIT;
4071 }
4072
4073 VEHICLE_DG("%s enter, cifirq_normal_idx(%ld) cif->frame_idx(%d)!\n", __func__,
4074 cif->irqinfo.cifirq_normal_idx, cif->frame_idx);
4075 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
4076 if (!cif->stopping) {
4077 if (cif->irqinfo.cifirq_normal_idx == cif->frame_idx) {
4078 cif->irqinfo.cifirq_abnormal_idx++;
4079 } else {
4080 cif->irqinfo.cifirq_normal_idx = cif->frame_idx;
4081 cif->irqinfo.cifirq_abnormal_idx = 0;
4082 }
4083 }
4084
4085 intstat = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_INTSTAT);
4086 lastline = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
4087
4088 /* clear all interrupts that has been triggered */
4089 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
4090
4091 /* when not detect new FRAME_END continue over 5 irq, reset, it's abnormal */
4092 if (cif->irqinfo.cifirq_abnormal_idx >= 5) {
4093 VEHICLE_DGERR(
4094 "ERROR: cifirq_abnormal_idx reach(%ld) consecutive, do reset work!!\n",
4095 cif->irqinfo.cifirq_abnormal_idx);
4096 // mod_delayed_work(system_wq, &cif->work,
4097 // msecs_to_jiffies(1));
4098 cif->irqinfo.cifirq_abnormal_idx = 0;
4099 vehicle_cif_stat_change_notify();
4100 goto IRQ_EXIT;
4101 }
4102
4103 if (intstat & CSI_FIFO_OVERFLOW) {
4104 cif->irqinfo.csi_overflow_cnt++;
4105 VEHICLE_DGERR(
4106 "ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
4107 intstat, lastline);
4108 goto IRQ_EXIT;
4109 }
4110
4111 if (intstat & CSI_BANDWIDTH_LACK) {
4112 cif->irqinfo.csi_bwidth_lack_cnt++;
4113 VEHICLE_DGERR(
4114 "ERROR: csi bandwidth lack, intstat:0x%x!!\n",
4115 intstat);
4116 if (cif->irqinfo.csi_bwidth_lack_cnt >= 5) {
4117 //do reset work
4118 // mod_delayed_work(system_wq, &cif->work,
4119 // msecs_to_jiffies(1));
4120 }
4121 goto IRQ_EXIT;
4122 }
4123
4124 if (intstat & CSI_ALL_ERROR_INTEN) {
4125 cif->irqinfo.all_err_cnt++;
4126 VEHICLE_DGERR(
4127 "ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
4128 goto IRQ_EXIT;
4129 }
4130
4131 /* if do not reach frame dma end, return irq */
4132 mipi_id = vehicle_cif_csi2_g_mipi_id(intstat);
4133 if (mipi_id < 0)
4134 goto IRQ_EXIT;
4135
4136 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
4137 mipi_id = vehicle_cif_csi2_g_mipi_id(intstat);
4138
4139 VEHICLE_DG(" i(%d) mipi_id(%d)\n", i, mipi_id);
4140 if (mipi_id < 0)
4141 continue;
4142
4143 if (cif->stopping) {
4144 vehicle_cif_csi2_s_stream(cif, 0, V4L2_MBUS_CSI2_DPHY);
4145 cif->stopping = false;
4146 wake_up(&cif->wq_stopped);
4147 continue;
4148 }
4149
4150 if (cif->state != RKCIF_STATE_STREAMING)
4151 continue;
4152
4153 switch (mipi_id) {
4154 case RKCIF_STREAM_MIPI_ID0:
4155 frame_phase = SW_FRM_END_ID0(intstat);
4156 intstat &= ~CSI_FRAME_END_ID0;
4157 break;
4158 case RKCIF_STREAM_MIPI_ID1:
4159 frame_phase = SW_FRM_END_ID1(intstat);
4160 intstat &= ~CSI_FRAME_END_ID1;
4161 break;
4162 case RKCIF_STREAM_MIPI_ID2:
4163 frame_phase = SW_FRM_END_ID2(intstat);
4164 intstat &= ~CSI_FRAME_END_ID2;
4165 break;
4166 case RKCIF_STREAM_MIPI_ID3:
4167 frame_phase = SW_FRM_END_ID3(intstat);
4168 intstat &= ~CSI_FRAME_END_ID3;
4169 break;
4170 }
4171
4172 if (frame_phase & CIF_CSI_FRAME1_READY)
4173 frame_ready = 1;
4174 else if (frame_phase & CIF_CSI_FRAME0_READY)
4175 frame_ready = 0;
4176
4177 addr = cif->active[frame_ready];
4178 if (vehicle_cif_next_buffer(cif, frame_ready, mipi_id) < 0)
4179 VEHICLE_DG("cif_nex_buffer error, do not commit %lx\n", addr);
4180 else
4181 vehicle_flinger_commit_cif_buffer(addr);
4182 }
4183 cif->frame_idx++;
4184 } else {
4185 intstat = rkcif_read_reg(cif, CIF_REG_DVP_INTSTAT);
4186 cif_frmst = rkcif_read_reg(cif, CIF_REG_DVP_FRAME_STATUS);
4187 lastline = rkcif_read_reg(cif, CIF_REG_DVP_LAST_LINE);
4188 lastline = CIF_FETCH_Y_LAST_LINE(lastline);
4189 lastpix = rkcif_read_reg(cif, CIF_REG_DVP_LAST_PIX);
4190 lastpix = CIF_FETCH_Y_LAST_LINE(lastpix);
4191 ctl = rkcif_read_reg(cif, CIF_REG_DVP_CTRL);
4192 VEHICLE_DG("lastline:%d, lastpix:%d, ctl:%d\n",
4193 lastline, lastpix, ctl);
4194
4195 rkcif_write_reg(cif, CIF_REG_DVP_INTSTAT, intstat);
4196
4197 if ((intstat & LINE_INT_END) && !(intstat & (FRAME_END))) {
4198 if ((intstat & (PRE_INF_FRAME_END | PST_INF_FRAME_END)) == 0x0) {
4199 if ((intstat & INTSTAT_ERR) == 0x0) {
4200 int_en = rkcif_read_reg(cif, CIF_REG_DVP_INTEN);
4201 int_en &= ~LINE_INT_EN;
4202 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, int_en);
4203 }
4204 }
4205 }
4206
4207 /* 0. error process */
4208 if (cif_irq_error_process(cif, intstat) < 0) {
4209 VEHICLE_DGERR("irq error, to do... reset, intstat=%x\n", intstat);
4210 // mod_delayed_work(system_wq, &cif->work,
4211 // msecs_to_jiffies(1));
4212 vehicle_cif_stat_change_notify();
4213 goto IRQ_EXIT;
4214 }
4215
4216 /* There are two irqs enabled:
4217 * - PST_INF_FRAME_END: cif FIFO is ready,
4218 * this is prior to FRAME_END
4219 * - FRAME_END: cif has saved frame to memory,
4220 * a frame ready
4221 */
4222 if ((intstat & PST_INF_FRAME_END)) {
4223 cif->irqinfo.cifirq_idx++;
4224 if (cif->stopping) {
4225 /* To stop CIF ASAP, before FRAME_END irq */
4226 vehicle_cif_s_stream(cif, 0);
4227 cif->stopping = false;
4228 wake_up(&cif->wq_stopped);
4229 goto IRQ_EXIT;
4230 }
4231 }
4232
4233 if ((intstat & FRAME_END)) {
4234 int_en = rkcif_read_reg(cif, CIF_REG_DVP_INTEN);
4235 int_en |= LINE_INT_EN;
4236 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, int_en);
4237
4238 if (cif->stopping) {
4239 vehicle_cif_s_stream(cif, 0);
4240 cif->stopping = false;
4241 wake_up(&cif->wq_stopped);
4242 goto IRQ_EXIT;
4243 }
4244
4245 frmid = CIF_GET_FRAME_ID(cif_frmst);
4246 if ((cif_frmst == 0xfffd0002) || (cif_frmst == 0xfffe0002)) {
4247 VEHICLE_DG("frmid:%d, frmstat:0x%x\n",
4248 frmid, cif_frmst);
4249 rkcif_write_reg(cif, CIF_REG_DVP_FRAME_STATUS,
4250 FRAME_STAT_CLS);
4251 }
4252
4253 if ((!(cif_frmst & CIF_F0_READY) && !(cif_frmst & CIF_F1_READY))) {
4254 VEHICLE_DG("err f0 && f1 not ready\n");
4255 cif_capture_en(cif->base, 0);
4256 rkcif_write_reg(cif, CIF_REG_DVP_INTEN, 0);
4257 mod_delayed_work(system_wq, &cif->work,
4258 msecs_to_jiffies(1));
4259 goto IRQ_EXIT;
4260 }
4261
4262 if (cif_frmst & CIF_F0_READY)
4263 frame_ready = 0;
4264 else
4265 frame_ready = 1;
4266 addr = cif->active[frame_ready];
4267 if (vehicle_cif_next_buffer(cif, frame_ready, mipi_id) < 0)
4268 CIF_DG("cif_nex_buffer error, do not commit %lx\n", addr);
4269 else
4270 vehicle_flinger_commit_cif_buffer(addr);
4271 cif->frame_idx++;
4272 }
4273 }
4274 cif->irqinfo.all_frm_end_cnt++;
4275
4276 IRQ_EXIT:
4277 return IRQ_HANDLED;
4278 }
4279
rk_camera_irq_v1(int irq,void * data)4280 static irqreturn_t rk_camera_irq_v1(int irq, void *data)
4281 {
4282 struct vehicle_cif *cif = (struct vehicle_cif *)data;
4283 u32 lastline;
4284 unsigned int intstat, i = 0xff, bak_intstat = 0;
4285 int frame_ready = 0;
4286 int frame_phase = 0;
4287 unsigned long addr;
4288 int mipi_id = 0;
4289
4290 if (drop_frames_number > 0) {
4291 VEHICLE_INFO("%s discard the first few frames!\n", __func__);
4292 drop_frames_number--;
4293 goto IRQ_EXIT;
4294 }
4295
4296 VEHICLE_DG("%s enter, cifirq_normal_idx(%ld) cif->frame_idx(%d)!\n", __func__,
4297 cif->irqinfo.cifirq_normal_idx, cif->frame_idx);
4298 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
4299 if (!cif->stopping) {
4300 if (cif->irqinfo.cifirq_normal_idx == cif->frame_idx) {
4301 cif->irqinfo.cifirq_abnormal_idx++;
4302 } else {
4303 cif->irqinfo.cifirq_normal_idx = cif->frame_idx;
4304 cif->irqinfo.cifirq_abnormal_idx = 0;
4305 }
4306 }
4307
4308 intstat = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_INTSTAT);
4309 lastline = rkcif_read_reg(cif, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
4310
4311 /* clear all interrupts that has been triggered */
4312 if (intstat) {
4313 bak_intstat = intstat;
4314 VEHICLE_DG("%s bak_intstat = %d!\n", __func__, bak_intstat);
4315 rkcif_write_reg(cif, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
4316 } else {
4317 goto IRQ_EXIT;
4318 }
4319
4320 /* when not detect new FRAME_END continue over 5 irq, reset, it's abnormal */
4321 if (cif->irqinfo.cifirq_abnormal_idx >= 5) {
4322 VEHICLE_DGERR(
4323 "ERROR: cifirq_abnormal_idx reach(%ld) consecutive, do reset work!!\n",
4324 cif->irqinfo.cifirq_abnormal_idx);
4325 cif->irqinfo.cifirq_abnormal_idx = 0;
4326 vehicle_cif_stat_change_notify();
4327 goto IRQ_EXIT;
4328 }
4329
4330 if (intstat & CSI_SIZE_ERR) {
4331 cif->irqinfo.csi_size_err_cnt++;
4332 VEHICLE_DGERR("ERROR: csi size error, intstat:0x%x, lastline:%d!!\n",
4333 intstat, lastline);
4334 goto IRQ_EXIT;
4335 }
4336
4337 if (intstat & CSI_FIFO_OVERFLOW_V1) {
4338 cif->irqinfo.csi_overflow_cnt++;
4339 VEHICLE_DGERR("ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
4340 intstat, lastline);
4341 goto IRQ_EXIT;
4342 }
4343
4344 if (intstat & CSI_BANDWIDTH_LACK_V1) {
4345 cif->irqinfo.csi_bwidth_lack_cnt++;
4346 VEHICLE_DGERR("ERROR: csi bandwidth lack, intstat:0x%x!!\n",
4347 intstat);
4348 goto IRQ_EXIT;
4349 }
4350
4351 if (intstat & CSI_ALL_ERROR_INTEN_V1) {
4352 cif->irqinfo.all_err_cnt++;
4353 VEHICLE_DGERR("ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
4354 goto IRQ_EXIT;
4355 }
4356
4357 /* if do not reach frame dma end, return irq */
4358 mipi_id = vehicle_cif_csi2_g_mipi_id(intstat);
4359 if (mipi_id < 0)
4360 goto IRQ_EXIT;
4361
4362 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
4363 mipi_id = vehicle_cif_csi2_g_mipi_id(intstat);
4364
4365 VEHICLE_DG(" i(%d) mipi_id(%d)\n", i, mipi_id);
4366 if (mipi_id < 0)
4367 continue;
4368
4369 if (cif->stopping) {
4370 vehicle_cif_csi2_s_stream_v1(cif, 0, V4L2_MBUS_CSI2_DPHY);
4371 cif->stopping = false;
4372 wake_up(&cif->wq_stopped);
4373 continue;
4374 }
4375
4376 if (cif->state != RKCIF_STATE_STREAMING)
4377 continue;
4378
4379 switch (mipi_id) {
4380 case RKCIF_STREAM_MIPI_ID0:
4381 frame_phase = SW_FRM_END_ID0(intstat);
4382 intstat &= ~CSI_FRAME_END_ID0;
4383 break;
4384 case RKCIF_STREAM_MIPI_ID1:
4385 frame_phase = SW_FRM_END_ID1(intstat);
4386 intstat &= ~CSI_FRAME_END_ID1;
4387 break;
4388 case RKCIF_STREAM_MIPI_ID2:
4389 frame_phase = SW_FRM_END_ID2(intstat);
4390 intstat &= ~CSI_FRAME_END_ID2;
4391 break;
4392 case RKCIF_STREAM_MIPI_ID3:
4393 frame_phase = SW_FRM_END_ID3(intstat);
4394 intstat &= ~CSI_FRAME_END_ID3;
4395 break;
4396 }
4397
4398 if (frame_phase & CIF_CSI_FRAME1_READY)
4399 frame_ready = 1;
4400 else if (frame_phase & CIF_CSI_FRAME0_READY)
4401 frame_ready = 0;
4402
4403 addr = cif->active[frame_ready];
4404 if (vehicle_cif_next_buffer(cif, frame_ready, mipi_id) < 0)
4405 VEHICLE_DGERR("cif_nex_buffer error, do not commit %lx\n", addr);
4406 else
4407 vehicle_flinger_commit_cif_buffer(addr);
4408 }
4409 cif->frame_idx++;
4410 } else {
4411 int ch_id;
4412
4413 intstat = rkcif_read_reg(cif, CIF_REG_DVP_INTSTAT);
4414
4415 rkcif_write_reg(cif, CIF_REG_DVP_INTSTAT, intstat);
4416
4417 if (intstat & DVP_SIZE_ERR) {
4418 cif->irqinfo.dvp_size_err_cnt++;
4419 VEHICLE_DGERR("dvp size err intstat 0x%x\n", intstat);
4420 }
4421
4422 if (intstat & DVP_FIFO_OVERFLOW) {
4423 cif->irqinfo.dvp_overflow_cnt++;
4424 VEHICLE_DGERR("dvp fifo overflow err intstat 0x%x\n", intstat);
4425 }
4426
4427 if (intstat & DVP_BANDWIDTH_LACK) {
4428 cif->irqinfo.dvp_bwidth_lack_cnt++;
4429 VEHICLE_DGERR("dvp bandwidth lack err intstat 0x%x\n", intstat);
4430 }
4431
4432 if (intstat & INTSTAT_ERR_RK3588) {
4433 cif->irqinfo.all_err_cnt++;
4434 VEHICLE_DGERR("ERROR: DVP_ALL_ERROR_INTEN:0x%x!!\n", intstat);
4435 }
4436 for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
4437 ch_id = rkcif_dvp_g_ch_id_by_fe(intstat);
4438
4439 if (ch_id < 0)
4440 continue;
4441
4442 if (cif->stopping) {
4443 vehicle_cif_s_stream(cif, 0);
4444 cif->stopping = false;
4445 wake_up(&cif->wq_stopped);
4446 continue;
4447 }
4448
4449 if (cif->state != RKCIF_STATE_STREAMING)
4450 continue;
4451
4452 switch (ch_id) {
4453 case RKCIF_STREAM_MIPI_ID0:
4454 frame_phase = SW_FRM_END_ID0(intstat);
4455 intstat &= ~DVP_ALL_END_ID0;
4456 break;
4457 case RKCIF_STREAM_MIPI_ID1:
4458 frame_phase = SW_FRM_END_ID1(intstat);
4459 intstat &= ~DVP_ALL_END_ID1;
4460 break;
4461 case RKCIF_STREAM_MIPI_ID2:
4462 frame_phase = SW_FRM_END_ID2(intstat);
4463 intstat &= ~DVP_ALL_END_ID2;
4464 break;
4465 case RKCIF_STREAM_MIPI_ID3:
4466 frame_phase = SW_FRM_END_ID3(intstat);
4467 intstat &= ~DVP_ALL_END_ID3;
4468 break;
4469 }
4470
4471 if (frame_phase & CIF_F0_READY)
4472 frame_ready = 0;
4473 else
4474 frame_ready = 1;
4475
4476 addr = cif->active[frame_ready];
4477 if (vehicle_cif_next_buffer(cif, frame_ready, ch_id) < 0)
4478 VEHICLE_DGERR("cif_nex_buffer error, do not commit %lx\n", addr);
4479 else
4480 vehicle_flinger_commit_cif_buffer(addr);
4481
4482 cif->frame_idx++;
4483 }
4484 }
4485 cif->irqinfo.all_frm_end_cnt++;
4486
4487 IRQ_EXIT:
4488 return IRQ_HANDLED;
4489 }
4490
4491 #define vehicle_csi2_err_strncat(dst_str, src_str) {\
4492 if (strlen(dst_str) + strlen(src_str) < CSI_ERRSTR_LEN)\
4493 strncat(dst_str, src_str, strlen(src_str)); }
4494
vehicle_csi2_find_err_vc(int val,char * vc_info)4495 static void vehicle_csi2_find_err_vc(int val, char *vc_info)
4496 {
4497 int i;
4498 char cur_str[CSI_VCINFO_LEN] = {0};
4499
4500 memset(vc_info, 0, sizeof(*vc_info));
4501 for (i = 0; i < 4; i++) {
4502 if ((val >> i) & 0x1) {
4503 snprintf(cur_str, CSI_VCINFO_LEN, " %d", i);
4504 if (strlen(vc_info) + strlen(cur_str) < CSI_VCINFO_LEN)
4505 strncat(vc_info, cur_str, strlen(cur_str));
4506 }
4507 }
4508 }
4509
vehicle_csi2_err_print_work(struct work_struct * work)4510 static void vehicle_csi2_err_print_work(struct work_struct *work)
4511 {
4512 struct vehicle_csi2_err_state_work *err_state = container_of(work,
4513 struct vehicle_csi2_err_state_work,
4514 work);
4515
4516 pr_err("mipi_csi2: ERR%d:0x%x %s\n", err_state->err_num,
4517 err_state->err_val, err_state->err_str);
4518 if (err_state->err_num == 1)
4519 pr_info("mipi_csi2: err_stat:0x%x\n", err_state->err_stat);
4520 }
4521
vehicle_csirx_irq1(int irq,void * data)4522 static irqreturn_t vehicle_csirx_irq1(int irq, void *data)
4523 {
4524 struct vehicle_cif *cif = (struct vehicle_cif *)data;
4525 struct csi2_dphy_hw *hw = cif->dphy_hw;
4526 struct csi2_err_stats *err_list = NULL;
4527 unsigned long err_stat = 0;
4528 u32 val;
4529 char err_str[CSI_ERRSTR_LEN] = {0};
4530 char cur_str[CSI_ERRSTR_LEN] = {0};
4531 char vc_info[CSI_VCINFO_LEN] = {0};
4532
4533 val = read_reg(hw->csi2_base, CSIHOST_ERR1);
4534 if (val) {
4535 write_reg(hw->csi2_base,
4536 CSIHOST_ERR1, 0x0);
4537
4538 if (val & CSIHOST_ERR1_PHYERR_SPTSYNCHS) {
4539 err_list = &hw->err_list[RK_CSI2_ERR_SOTSYN];
4540 err_list->cnt++;
4541
4542 vehicle_csi2_find_err_vc(val & 0xf, vc_info);
4543 snprintf(cur_str, CSI_ERRSTR_LEN, "(sot sync,lane:%s) ", vc_info);
4544 vehicle_csi2_err_strncat(err_str, cur_str);
4545 }
4546
4547 if (val & CSIHOST_ERR1_ERR_BNDRY_MATCH) {
4548 err_list = &hw->err_list[RK_CSI2_ERR_FS_FE_MIS];
4549 err_list->cnt++;
4550 vehicle_csi2_find_err_vc((val >> 4) & 0xf, vc_info);
4551 snprintf(cur_str, CSI_ERRSTR_LEN, "(fs/fe miss,vc:%s) ", vc_info);
4552 vehicle_csi2_err_strncat(err_str, cur_str);
4553
4554 }
4555
4556 if (val & CSIHOST_ERR1_ERR_SEQ) {
4557 err_list = &hw->err_list[RK_CSI2_ERR_FRM_SEQ_ERR];
4558 err_list->cnt++;
4559 vehicle_csi2_find_err_vc((val >> 8) & 0xf, vc_info);
4560 snprintf(cur_str, CSI_ERRSTR_LEN, "(f_seq,vc:%s) ", vc_info);
4561 vehicle_csi2_err_strncat(err_str, cur_str);
4562
4563 }
4564
4565 if (val & CSIHOST_ERR1_ERR_FRM_DATA) {
4566 err_list = &hw->err_list[RK_CSI2_ERR_CRC_ONCE];
4567 err_list->cnt++;
4568 vehicle_csi2_find_err_vc((val >> 12) & 0xf, vc_info);
4569 snprintf(cur_str, CSI_ERRSTR_LEN, "(err_data,vc:%s) ", vc_info);
4570 vehicle_csi2_err_strncat(err_str, cur_str);
4571
4572 }
4573
4574 if (val & CSIHOST_ERR1_ERR_CRC) {
4575 err_list = &hw->err_list[RK_CSI2_ERR_CRC];
4576 err_list->cnt++;
4577 vehicle_csi2_find_err_vc((val >> 24) & 0xf, vc_info);
4578 snprintf(cur_str, CSI_ERRSTR_LEN, "(crc,vc:%s) ", vc_info);
4579 vehicle_csi2_err_strncat(err_str, cur_str);
4580
4581 }
4582
4583 if (val & CSIHOST_ERR1_ERR_ECC2) {
4584 err_list = &hw->err_list[RK_CSI2_ERR_CRC];
4585 err_list->cnt++;
4586 snprintf(cur_str, CSI_ERRSTR_LEN, "(ecc2) ");
4587 vehicle_csi2_err_strncat(err_str, cur_str);
4588
4589 }
4590 if (val & CSIHOST_ERR1_ERR_CTRL) {
4591 vehicle_csi2_find_err_vc((val >> 16) & 0xf, vc_info);
4592 snprintf(cur_str, CSI_ERRSTR_LEN, "(ctrl,vc:%s) ", vc_info);
4593 vehicle_csi2_err_strncat(err_str, cur_str);
4594 }
4595 hw->err_list[RK_CSI2_ERR_ALL].cnt++;
4596 err_stat = ((hw->err_list[RK_CSI2_ERR_FS_FE_MIS].cnt & 0xff) << 8) |
4597 ((hw->err_list[RK_CSI2_ERR_ALL].cnt) & 0xff);
4598
4599 cif->err_state.err_val = val;
4600 cif->err_state.err_num = 1;
4601 cif->err_state.err_stat = err_stat;
4602 strscpy(cif->err_state.err_str, err_str, CSI_ERRSTR_LEN);
4603 queue_work(cif->err_state.err_print_wq, &cif->err_state.work);
4604
4605 }
4606
4607 return IRQ_HANDLED;
4608 }
4609
vehicle_csirx_irq2(int irq,void * data)4610 static irqreturn_t vehicle_csirx_irq2(int irq, void *data)
4611 {
4612 struct vehicle_cif *cif = (struct vehicle_cif *)data;
4613 struct csi2_dphy_hw *hw = cif->dphy_hw;
4614 u32 val;
4615 char cur_str[CSI_ERRSTR_LEN] = {0};
4616 char err_str[CSI_ERRSTR_LEN] = {0};
4617 char vc_info[CSI_VCINFO_LEN] = {0};
4618
4619 val = read_reg(hw->csi2_base, CSIHOST_ERR2);
4620 if (val) {
4621 if (val & CSIHOST_ERR2_PHYERR_ESC) {
4622 vehicle_csi2_find_err_vc(val & 0xf, vc_info);
4623 snprintf(cur_str, CSI_ERRSTR_LEN, "(ULPM,lane:%s) ", vc_info);
4624 vehicle_csi2_err_strncat(err_str, cur_str);
4625 }
4626 if (val & CSIHOST_ERR2_PHYERR_SOTHS) {
4627 vehicle_csi2_find_err_vc((val >> 4) & 0xf, vc_info);
4628 snprintf(cur_str, CSI_ERRSTR_LEN, "(sot,lane:%s) ", vc_info);
4629 vehicle_csi2_err_strncat(err_str, cur_str);
4630 }
4631 if (val & CSIHOST_ERR2_ECC_CORRECTED) {
4632 vehicle_csi2_find_err_vc((val >> 8) & 0xf, vc_info);
4633 snprintf(cur_str, CSI_ERRSTR_LEN, "(ecc,vc:%s) ", vc_info);
4634 vehicle_csi2_err_strncat(err_str, cur_str);
4635 }
4636 if (val & CSIHOST_ERR2_ERR_ID) {
4637 vehicle_csi2_find_err_vc((val >> 12) & 0xf, vc_info);
4638 snprintf(cur_str, CSI_ERRSTR_LEN, "(err id,vc:%s) ", vc_info);
4639 vehicle_csi2_err_strncat(err_str, cur_str);
4640 }
4641 if (val & CSIHOST_ERR2_PHYERR_CODEHS) {
4642 snprintf(cur_str, CSI_ERRSTR_LEN, "(err code) ");
4643 vehicle_csi2_err_strncat(err_str, cur_str);
4644 }
4645 cif->err_state.err_val = val;
4646 cif->err_state.err_num = 2;
4647 strscpy(cif->err_state.err_str, err_str, CSI_ERRSTR_LEN);
4648 queue_work(cif->err_state.err_print_wq, &cif->err_state.work);
4649
4650 }
4651
4652 return IRQ_HANDLED;
4653 }
4654
vehicle_cif_reverse_open(struct vehicle_cfg * v_cfg)4655 int vehicle_cif_reverse_open(struct vehicle_cfg *v_cfg)
4656 {
4657 int ret = 0;
4658 struct vehicle_cif *cif = g_cif;
4659
4660 if (!cif)
4661 return -ENODEV;
4662
4663 mutex_lock(&cif->stream_lock);
4664 memcpy(&cif->cif_cfg, v_cfg, sizeof(struct vehicle_cfg));
4665 ret = pm_runtime_get_sync(cif->dev);
4666 if (ret < 0) {
4667 pm_runtime_put_noidle(cif->dev);
4668 VEHICLE_DGERR("%s pm_runtime_get_sync failed\n", __func__);
4669 goto exit;
4670 }
4671
4672 /*get dcphy param*/
4673 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588_DCPHY) {
4674 if (cif->cif_cfg.dphy_param) {
4675 cif->dphy_hw->dphy_param = cif->cif_cfg.dphy_param;
4676 dev_info(cif->dev, "-----get dphy param from sensor----\n");
4677 } else {
4678 cif->dphy_hw->dphy_param = &rk3588_dcphy_param;
4679 dev_info(cif->dev, "fail to get dphy param, used default value\n");
4680 }
4681 }
4682 /* set ddr fix freq */
4683 rockchip_set_system_status(SYS_STATUS_CIF0);
4684 vehicle_cif_hw_soft_reset(cif);
4685 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
4686 /* 0. set mipi-dphy data rate */
4687 cif->dphy_hw->data_rate_mbps = cif->cif_cfg.mipi_freq * 2 / 1000 / 1000;
4688
4689 /* 0. set csi2 & dphy clk */
4690 vehicle_csi2_hw_soft_reset(cif);
4691 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588)
4692 vehicle_csi2_dphy_hw_do_reset(cif);
4693
4694 if (!cif->dphy_hw->on)
4695 vehicle_csi2_clk_ctrl(cif, 1);
4696
4697 /* 1. stream setup */
4698 cif_csi_stream_setup(cif);
4699
4700 /* 2. create dummy buf */
4701 ret = vehicle_cif_create_dummy_buf(cif);
4702 if (ret < 0)
4703 VEHICLE_DGERR("Failed to create dummy_buf, %d\n", ret);
4704
4705 /* 3. cif init buffer */
4706 if (vehicle_cif_init_buffer(cif, 1, cif->channels[0].id) < 0)
4707 goto exit;
4708
4709 /* 4. dump cif regs */
4710 vehicle_cif_csi2_dump_regs(cif);
4711
4712 /* 5. start stream */
4713 if (cif->chip_id >= CHIP_RK3588_VEHICLE_CIF)
4714 vehicle_cif_csi2_s_stream_v1(cif, 1, V4L2_MBUS_CSI2_DPHY);
4715 else
4716 vehicle_cif_csi2_s_stream(cif, 1, V4L2_MBUS_CSI2_DPHY);
4717
4718 } else {
4719 /* 1. stream setup */
4720 cif_stream_setup(cif);
4721
4722 /* 2. create dummy buf */
4723 ret = vehicle_cif_create_dummy_buf(cif);
4724 if (ret < 0)
4725 VEHICLE_DGERR("Failed to create dummy_buf, %d\n", ret);
4726
4727 /* 2. cif init buffer */
4728 if (vehicle_cif_init_buffer(cif, 1, 0) < 0)
4729 goto exit;
4730
4731 /* 3. enable interrupts */
4732 if (cif->chip_id < CHIP_RK3588_VEHICLE_CIF)
4733 cif_interrupt_setup(cif);
4734
4735 /* 4. dump cif regs */
4736 vehicle_cif_dvp_dump_regs(cif);
4737
4738 /* 5. start stream */
4739 vehicle_cif_s_stream(cif, 1);
4740 }
4741
4742 cif->stopping = false;
4743 drop_frames_number = cif->drop_frames;
4744
4745 mutex_unlock(&cif->stream_lock);
4746
4747 return 0;
4748
4749 exit:
4750 mutex_unlock(&cif->stream_lock);
4751 return -1;
4752 }
4753
vehicle_cif_reverse_close(void)4754 int vehicle_cif_reverse_close(void)
4755 {
4756 int ret = 0;
4757 struct vehicle_cif *cif = g_cif;
4758
4759 if (!cif)
4760 return -ENODEV;
4761
4762 mutex_lock(&cif->stream_lock);
4763
4764 VEHICLE_DG("%s cif reverse start closing\n", __func__);
4765 cif->stopping = true;
4766 cancel_delayed_work_sync(&(cif->work));
4767 flush_delayed_work(&(cif->work));
4768 cancel_work_sync(&cif->err_state.work);
4769
4770 ret = wait_event_timeout(cif->wq_stopped,
4771 cif->state != RKCIF_STATE_STREAMING,
4772 msecs_to_jiffies(100));
4773 if (!ret) {
4774 VEHICLE_DGERR("%s wait stream stop timeout!\n", __func__);
4775 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
4776 if (cif->chip_id >= CHIP_RK3588_VEHICLE_CIF)
4777 vehicle_cif_csi2_s_stream_v1(cif, 0, V4L2_MBUS_CSI2_DPHY);
4778 else
4779 vehicle_cif_csi2_s_stream(cif, 0, V4L2_MBUS_CSI2_DPHY);
4780 } else {
4781 vehicle_cif_s_stream(cif, 0);
4782 }
4783 //cif->stopping = false;
4784 }
4785 if (cif->cif_cfg.type == V4L2_MBUS_CSI2_DPHY) {
4786 vehicle_cif_csi_stream_stop(cif);
4787 vehicle_csi2_hw_soft_reset(cif);
4788 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588)
4789 vehicle_csi2_dphy_hw_do_reset(cif);
4790 if (cif->dphy_hw->on)
4791 vehicle_csi2_clk_ctrl(cif, 0);
4792 }
4793
4794 vehicle_cif_destroy_dummy_buf(cif);
4795 //vehicle_csi2_hw_soft_reset(cif);
4796 //vehicle_cif_hw_soft_reset(cif);
4797 rockchip_clear_system_status(SYS_STATUS_CIF0);
4798 mutex_unlock(&cif->stream_lock);
4799 cif->stopping = false;
4800
4801 return 0;
4802 }
4803
vehicle_cif_dphy_get_node(struct vehicle_cif * cif)4804 static void vehicle_cif_dphy_get_node(struct vehicle_cif *cif)
4805 {
4806 struct device_node *node = NULL;
4807 struct device_node *cp = NULL;
4808 struct device *dev = cif->dev;
4809 const char *status = NULL;
4810
4811 node = of_parse_phandle(dev->of_node, "rockchip,cif-phy", 0);
4812 if (!node) {
4813 VEHICLE_DGERR("get cif-phy dts failed\n");
4814 return;
4815 }
4816
4817 for_each_child_of_node(node, cp) {
4818 of_property_read_string(cp, "status", &status);
4819 if (status && !strcmp(status, "disabled"))
4820 continue;
4821 else
4822 cif->phy_node = cp;
4823 VEHICLE_INFO("status: %s %s\n", cp->name, status);
4824 }
4825 }
4826
cif_parse_dt(struct vehicle_cif * cif)4827 static int cif_parse_dt(struct vehicle_cif *cif)
4828 {
4829 struct device *dev = cif->dev;
4830 struct device_node *node;
4831 struct device_node *phy_node = cif->phy_node;
4832 struct device_node *cif_node;
4833 struct device_node *cis2_node;
4834
4835 if (of_property_read_u32(dev->of_node, "cif,drop-frames",
4836 &cif->drop_frames)) {
4837 VEHICLE_INFO("%s:Get cif, drop-frames failed!\n", __func__);
4838 cif->drop_frames = 0; //default drop frames;
4839 }
4840
4841 if (of_property_read_u32(dev->of_node, "cif,chip-id",
4842 &cif->chip_id)) {
4843 VEHICLE_INFO("%s:Get cif, chip_id failed!\n", __func__);
4844 cif->chip_id = CHIP_RK3588_VEHICLE_CIF; //default rk3588;
4845 }
4846
4847 cif_node = of_parse_phandle(dev->of_node, "rockchip,cif", 0);
4848 cif->base = (char *)of_iomap(cif_node, 0);
4849
4850 node = of_parse_phandle(dev->of_node, "rockchip,cru", 0);
4851 cif->cru_base = of_iomap(node, 0);
4852
4853 node = of_parse_phandle(dev->of_node, "rockchip,grf", 0);
4854 cif->grf_base = of_iomap(node, 0);
4855
4856 cif->regmap_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
4857 if (IS_ERR(cif->regmap_grf))
4858 VEHICLE_DGERR("unable to get rockchip,grf\n");
4859
4860 cif->irq = irq_of_parse_and_map(cif_node, 0);
4861 if (cif->irq < 0) {
4862 VEHICLE_DGERR("%s: request cif irq failed\n", __func__);
4863 iounmap(cif->base);
4864 iounmap(cif->cru_base);
4865 iounmap(cif->grf_base);
4866 return -ENODEV;
4867 }
4868
4869 if (of_property_read_u32(phy_node, "csihost-idx", &cif->csi_host_idx)) {
4870 VEHICLE_INFO("Get %s csihost-idx failed! sensor link to dvp!!\n",
4871 phy_node->name);
4872 cif->inf_id = RKCIF_DVP;
4873 } else {
4874 cif->inf_id = RKCIF_MIPI_LVDS;
4875 VEHICLE_INFO("sensor link to %s!!\n", phy_node->name);
4876 }
4877
4878 if (cif->inf_id == RKCIF_MIPI_LVDS) {
4879 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF &&
4880 !(cif->csi_host_idx == RKCIF_MIPI0_CSI2 ||
4881 cif->csi_host_idx == RKCIF_MIPI1_CSI2)) {
4882 node = of_parse_phandle(phy_node, "rockchip,csi2-dphy", 0);
4883 cif->csi2_dphy_base = of_iomap(node, 0);
4884
4885 cif->regmap_dphy_grf =
4886 syscon_regmap_lookup_by_phandle(phy_node, "rockchip,dphy-grf");
4887 if (IS_ERR(cif->regmap_dphy_grf))
4888 VEHICLE_INFO("unable to get rockchip,dphy-grf\n");
4889 } else if (cif->chip_id != CHIP_RK3588_VEHICLE_CIF) {
4890 node = of_parse_phandle(phy_node, "rockchip,csi2-dphy", 0);
4891 cif->csi2_dphy_base = of_iomap(node, 0);
4892 }
4893
4894 cis2_node = of_parse_phandle(phy_node, "rockchip,csi2", 0);
4895 cif->csi2_base = of_iomap(cis2_node, 0);
4896
4897 cif->csi2_irq1 = irq_of_parse_and_map(cis2_node, 0);
4898 if (cif->csi2_irq1 < 0) {
4899 VEHICLE_DGERR("%s: request csi-intr1 failed\n", __func__);
4900 iounmap(cif->base);
4901 iounmap(cif->cru_base);
4902 iounmap(cif->grf_base);
4903 iounmap(cif->csi2_dphy_base);
4904 iounmap(cif->csi2_base);
4905 return -ENODEV;
4906 }
4907
4908 cif->csi2_irq2 = irq_of_parse_and_map(cis2_node, 1);
4909 if (cif->csi2_irq2 < 0) {
4910 VEHICLE_DGERR("%s: request csi-intr2 failed\n", __func__);
4911 iounmap(cif->base);
4912 iounmap(cif->cru_base);
4913 iounmap(cif->grf_base);
4914 iounmap(cif->csi2_dphy_base);
4915 iounmap(cif->csi2_base);
4916 return -ENODEV;
4917 }
4918 }
4919
4920 VEHICLE_DG("%s, drop_frames = %d\n", __func__, cif->drop_frames);
4921
4922 return 0;
4923 }
4924
vehicle_cif_init_mclk(struct vehicle_cif * cif)4925 int vehicle_cif_init_mclk(struct vehicle_cif *cif)
4926 {
4927 struct device *dev = cif->dev;
4928 struct rk_cif_clk *clk = &cif->clk;
4929
4930 /* sensor MCLK:
4931 * current use CLK_CIF_OUT
4932 */
4933 vehicle_cif_dphy_get_node(cif);
4934 clk->xvclk = of_clk_get_by_name(cif->phy_node, "xvclk");
4935 if (IS_ERR(clk->xvclk)) {
4936 dev_err(dev, "Failed to get sensor xvclk\n");
4937 return -EINVAL;
4938 }
4939
4940 rkcif_s_mclk(cif, 1, 24000000);
4941 VEHICLE_INFO("%s(%d): set sensor MCLK rate 24MHZ OK!\n", __func__, __LINE__);
4942
4943 return 0;
4944 }
4945
vehicle_cif_deinit_mclk(struct vehicle_cif * cif)4946 static int vehicle_cif_deinit_mclk(struct vehicle_cif *cif)
4947 {
4948 struct rk_cif_clk *clk = &cif->clk;
4949
4950 /* release sensor MCLK:
4951 * current use CLK_CIF_OUT
4952 */
4953 if (!IS_ERR(clk->xvclk))
4954 clk_disable_unprepare(clk->xvclk);
4955 clk_put(clk->xvclk);
4956
4957 return 0;
4958 }
4959
vehicle_cif_init(struct vehicle_cif * cif)4960 int vehicle_cif_init(struct vehicle_cif *cif)
4961 {
4962 int ret;
4963 struct device *dev;
4964 struct rk_cif_clk *clk;
4965 struct csi2_dphy_hw *dphy_hw;
4966 struct clk *tmp_cif_clk = NULL;
4967 int i;
4968 int inf_id;
4969
4970 if (!cif)
4971 return -ENODEV;
4972
4973 dev = cif->dev;
4974 clk = &cif->clk;
4975 g_cif = cif;
4976
4977 /* 0. dts parse */
4978 if (cif_parse_dt(cif) < -1) {
4979 VEHICLE_DGERR("%s: cif_parse_dt failed\n", __func__);
4980 return -ENODEV;
4981 }
4982
4983 inf_id = cif->inf_id;
4984 if (inf_id == RKCIF_MIPI_LVDS) {
4985 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
4986 if (cif->csi_host_idx == RKCIF_MIPI0_CSI2 ||
4987 cif->csi_host_idx == RKCIF_MIPI1_CSI2)
4988 dphy_hw = &rk3588_csi2_dcphy_hw;
4989 else
4990 dphy_hw = &rk3588_csi2_dphy_hw;
4991 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
4992 dphy_hw = &rk3562_csi2_dphy_hw;
4993 } else {
4994 dphy_hw = &rk3568_csi2_dphy_hw;
4995 }
4996 }
4997
4998 /* 1. cif/csi2-dphy/csi2 clk setup */
4999 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
5000 clk->clks_num = ARRAY_SIZE(rk3588_cif_clks);
5001 clk->rsts_num = ARRAY_SIZE(rk3588_cif_rsts);
5002 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
5003 clk->clks_num = ARRAY_SIZE(rk3562_cif_clks);
5004 clk->rsts_num = ARRAY_SIZE(rk3562_cif_rsts);
5005 } else {
5006 clk->clks_num = ARRAY_SIZE(rk3568_cif_clks);
5007 clk->rsts_num = ARRAY_SIZE(rk3568_cif_rsts);
5008 }
5009
5010 if (inf_id == RKCIF_MIPI_LVDS) {
5011 cif->dphy_hw = dphy_hw;
5012 dphy_hw->dev = cif->dev;
5013 /*get phy_index*/
5014 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588) {
5015 if (cif->csi_host_idx >= RKCIF_MIPI4_CSI2)
5016 cif->dphy_hw->phy_index = 3;
5017 else
5018 cif->dphy_hw->phy_index = 0;
5019 } else if (cif->dphy_hw->chip_id == CHIP_ID_RK3562) {
5020 if (cif->csi_host_idx >= RKCIF_MIPI2_CSI2)
5021 cif->dphy_hw->phy_index = 3;
5022 else
5023 cif->dphy_hw->phy_index = 0;
5024 } else {
5025 cif->dphy_hw->phy_index = 0;
5026 }
5027 /*get mipi dcphy*/
5028 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588_DCPHY) {
5029 struct phy *dcphy = NULL;
5030 struct samsung_mipi_dcphy *dcphy_hw = NULL;
5031
5032 dcphy = of_phy_get(cif->phy_node, "dcphy");
5033 if (IS_ERR(dcphy)) {
5034 ret = PTR_ERR(dcphy);
5035 dev_err(dev, "failed to get mipi dcphy: %d\n", ret);
5036 return ret;
5037 }
5038 dcphy_hw = phy_get_drvdata(dcphy);
5039 dcphy_hw->dphy_vehicle[dcphy_hw->dphy_vehicle_num] = cif->dphy_hw;
5040 dcphy_hw->dphy_vehicle_num++;
5041 cif->dphy_hw->samsung_phy = dcphy_hw;
5042 }
5043 /* csi2 mipidphy rsts */
5044 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588 ||
5045 cif->dphy_hw->chip_id == CHIP_ID_RK3562) {
5046 for (i = 0; i < dphy_hw->num_dphy_rsts; i++) {
5047 struct reset_control *rst = NULL;
5048
5049 rst = of_reset_control_get(cif->phy_node, dphy_hw->dphy_rsts[i]);
5050 if (IS_ERR(rst)) {
5051 dev_err(dev, "failed to get %s\n", dphy_hw->dphy_rsts[i]);
5052 return PTR_ERR(rst);
5053 }
5054 dphy_hw->dphy_rst[i] = rst;
5055 }
5056 } else {
5057 dev_info(dev, "use mipi dcphy, no need request rst\n");
5058 }
5059
5060 /* csi2 mipidphy clks */
5061 for (i = 0; i < dphy_hw->num_dphy_clks; i++) {
5062 struct clk *tmp_clk =
5063 of_clk_get_by_name(cif->phy_node, dphy_hw->dphy_clks[i].id);
5064
5065 if (IS_ERR(tmp_clk)) {
5066 dev_err(dev, "failed to get %s\n", dphy_hw->dphy_clks[i].id);
5067 return PTR_ERR(tmp_clk);
5068 }
5069 dev_info(dev, "clk get %s\n", dphy_hw->dphy_clks[i].id);
5070 dphy_hw->dphy_clks[i].clk = tmp_clk;
5071 }
5072
5073 /* csi2 clks */
5074 for (i = 0; i < dphy_hw->num_csi2_clks; i++) {
5075 struct clk *tmp_clk =
5076 of_clk_get_by_name(cif->phy_node, dphy_hw->csi2_clks[i].id);
5077
5078 if (IS_ERR(tmp_clk)) {
5079 dev_err(dev, "failed to get %s\n", dphy_hw->csi2_clks[i].id);
5080 return PTR_ERR(tmp_clk);
5081 }
5082 dev_info(dev, "clk get %s\n", dphy_hw->csi2_clks[i].id);
5083 dphy_hw->csi2_clks[i].clk = tmp_clk;
5084 }
5085
5086 /* csi2 rsts */
5087 for (i = 0; i < dphy_hw->num_csi2_rsts; i++) {
5088 struct reset_control *rst = NULL;
5089
5090 rst = of_reset_control_get(cif->phy_node, dphy_hw->csi2_rsts[i]);
5091 if (IS_ERR(rst)) {
5092 dev_err(dev, "failed to get %s\n", dphy_hw->csi2_rsts[i]);
5093 return PTR_ERR(rst);
5094 }
5095 dphy_hw->csi2_rst[i] = rst;
5096 }
5097 dphy_hw->on = false;
5098 }
5099 /* vicap clks */
5100 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
5101 for (i = 0; i < clk->clks_num; i++) {
5102 tmp_cif_clk = devm_clk_get(dev, rk3588_cif_clks[i]);
5103
5104 if (IS_ERR(tmp_cif_clk)) {
5105 dev_err(dev, "failed to get %s\n", rk3588_cif_clks[i]);
5106 return PTR_ERR(tmp_cif_clk);
5107 }
5108 clk->clks[i] = tmp_cif_clk;
5109 clk->on = false;
5110 }
5111 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
5112 for (i = 0; i < clk->clks_num; i++) {
5113 tmp_cif_clk = devm_clk_get(dev, rk3562_cif_clks[i]);
5114
5115 if (IS_ERR(tmp_cif_clk)) {
5116 dev_err(dev, "failed to get %s\n", rk3562_cif_clks[i]);
5117 return PTR_ERR(tmp_cif_clk);
5118 }
5119 clk->clks[i] = tmp_cif_clk;
5120 clk->on = false;
5121 }
5122 } else {
5123 for (i = 0; i < clk->clks_num; i++) {
5124 tmp_cif_clk = devm_clk_get(dev, rk3568_cif_clks[i]);
5125
5126 if (IS_ERR(tmp_cif_clk)) {
5127 dev_err(dev, "failed to get %s\n", rk3568_cif_clks[i]);
5128 return PTR_ERR(tmp_cif_clk);
5129 }
5130 clk->clks[i] = tmp_cif_clk;
5131 clk->on = false;
5132 }
5133 }
5134
5135 /* vicap rsts */
5136 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
5137 for (i = 0; i < clk->rsts_num; i++) {
5138 struct reset_control *rst = NULL;
5139
5140 if (rk3568_cif_rsts[i])
5141 rst = devm_reset_control_get(dev, rk3588_cif_rsts[i]);
5142 if (IS_ERR(rst)) {
5143 dev_err(dev, "failed to get %s\n", rk3588_cif_rsts[i]);
5144 return PTR_ERR(rst);
5145 }
5146 clk->cif_rst[i] = rst;
5147 }
5148 } else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF) {
5149 for (i = 0; i < clk->rsts_num; i++) {
5150 struct reset_control *rst = NULL;
5151
5152 if (rk3568_cif_rsts[i])
5153 rst = devm_reset_control_get(dev, rk3562_cif_rsts[i]);
5154 if (IS_ERR(rst)) {
5155 dev_err(dev, "failed to get %s\n", rk3562_cif_rsts[i]);
5156 return PTR_ERR(rst);
5157 }
5158 clk->cif_rst[i] = rst;
5159 }
5160 } else {
5161 for (i = 0; i < clk->rsts_num; i++) {
5162 struct reset_control *rst = NULL;
5163
5164 if (rk3568_cif_rsts[i])
5165 rst = devm_reset_control_get(dev, rk3568_cif_rsts[i]);
5166 if (IS_ERR(rst)) {
5167 dev_err(dev, "failed to get %s\n", rk3568_cif_rsts[i]);
5168 return PTR_ERR(rst);
5169 }
5170 clk->cif_rst[i] = rst;
5171 }
5172 }
5173
5174 /* 2. set cif clk & sensor mclk */
5175 rk_cif_mclk_ctrl(cif, 1, 24000000);
5176 INIT_DELAYED_WORK(&cif->work, vehicle_cif_reset_work_func);
5177
5178 if (inf_id == RKCIF_MIPI_LVDS)
5179 /* 2. set csi2 & dphy clk */
5180 if (!cif->dphy_hw->on)
5181 vehicle_csi2_clk_ctrl(cif, 1);
5182
5183 /* 3. request cif irq & mipi csi irq1-2 */
5184 if (cif->chip_id >= CHIP_RK3588_VEHICLE_CIF) {
5185 ret = request_irq(cif->irq, rk_camera_irq_v1, IRQF_SHARED, "vehicle_cif", cif);
5186 if (ret < 0) {
5187 VEHICLE_DGERR("request cif irq failed!\n");
5188 return -EINVAL;
5189 }
5190 } else {
5191 ret = request_irq(cif->irq, rk_camera_irq, IRQF_SHARED, "vehicle_cif", cif);
5192 if (ret < 0) {
5193 VEHICLE_DGERR("request cif irq failed!\n");
5194 return -EINVAL;
5195 }
5196 }
5197
5198 VEHICLE_DG("%s(%d):\n", __func__, __LINE__);
5199
5200 if (inf_id == RKCIF_MIPI_LVDS) {
5201 ret = request_irq(cif->csi2_irq1, vehicle_csirx_irq1,
5202 IRQF_SHARED, "vehicle_csi_intr1", cif);
5203 if (ret < 0) {
5204 VEHICLE_DGERR("request csirx irq1 failed!\n");
5205 return -EINVAL;
5206 }
5207
5208 ret = request_irq(cif->csi2_irq2, vehicle_csirx_irq2,
5209 IRQF_SHARED, "vehicle_csi_intr2", cif);
5210 if (ret < 0) {
5211 VEHICLE_DGERR("request csirx irq2 failed!\n");
5212 return -EINVAL;
5213 }
5214 }
5215 /* 4. set cif regs */
5216 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF)
5217 cif->cif_regs = rk3588_cif_regs;
5218 else if (cif->chip_id == CHIP_RK3562_VEHICLE_CIF)
5219 cif->cif_regs = rk3562_cif_regs;
5220 else
5221 cif->cif_regs = rk3568_cif_regs;
5222
5223 if (inf_id == RKCIF_MIPI_LVDS) {
5224 /* 5. set csi2-mipi-dphy reg */
5225 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588 ||
5226 cif->dphy_hw->chip_id == CHIP_ID_RK3562)
5227 cif->dphy_hw->csi2_dphy_base = cif->csi2_dphy_base;
5228
5229 /* 7. set mipi-csi2 reg */
5230 cif->dphy_hw->csi2_base = cif->csi2_base;
5231
5232 /* 8. set dphy grf regmap */
5233 if (cif->chip_id == CHIP_RK3588_VEHICLE_CIF) {
5234 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588) {
5235 cif->dphy_hw->regmap_grf = cif->regmap_dphy_grf;
5236 cif->dphy_hw->regmap_sys_grf = cif->regmap_grf;
5237 }
5238 } else {
5239 cif->dphy_hw->regmap_grf = cif->regmap_grf;
5240 }
5241 mutex_init(&dphy_hw->mutex);
5242 }
5243 /* 9. init waitqueue */
5244 atomic_set(&cif->reset_status, 0);
5245 init_waitqueue_head(&cif->wq_stopped);
5246
5247 spin_lock_init(&cif->vbq_lock);
5248
5249 INIT_WORK(&cif->err_state.work, vehicle_csi2_err_print_work);
5250 cif->err_state.err_print_wq = create_workqueue("cis2_err_print_queue");
5251 if (cif->err_state.err_print_wq == NULL) {
5252 dev_err(dev, "%s: %s create failed.\n", __func__,
5253 "csi2_err_print_wq");
5254 }
5255
5256 return 0;
5257 }
5258
vehicle_cif_deinit(struct vehicle_cif * cif)5259 int vehicle_cif_deinit(struct vehicle_cif *cif)
5260 {
5261 struct rk_cif_clk *clk = &cif->clk;
5262 struct device *dev = cif->dev;
5263 int i;
5264 struct csi2_dphy_hw *dphy_hw = cif->dphy_hw;
5265 int inf_id = cif->inf_id;
5266
5267 // vehicle_cif_s_stream(cif, 0);
5268 // vehicle_cif_do_stop_stream(cif);
5269
5270 /* set csi2-dphy csi cif clk & sensor mclk */
5271 rk_cif_mclk_ctrl(cif, 0, 0);
5272 if (inf_id == RKCIF_MIPI_LVDS)
5273 if (cif->dphy_hw->on)
5274 vehicle_csi2_clk_ctrl(cif, 0);
5275
5276 /* release sensor MCLK */
5277 vehicle_cif_deinit_mclk(cif);
5278
5279 /* vicap rsts release */
5280 for (i = 0; i < clk->rsts_num; i++)
5281 reset_control_put(clk->cif_rst[i]);
5282
5283 /* vicap clk release */
5284 for (i = 0; i < clk->clks_num; i++)
5285 devm_clk_put(dev, clk->clks[i]);
5286
5287 if (inf_id == RKCIF_MIPI_LVDS) {
5288 /*dcphy put*/
5289 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588_DCPHY) {
5290 struct samsung_mipi_dcphy *dcphy_hw = cif->dphy_hw->samsung_phy;
5291 struct csi2_dphy_hw *csi2_dphy = NULL;
5292
5293 for (i = 0; i < dcphy_hw->dphy_vehicle_num; i++) {
5294 csi2_dphy = dcphy_hw->dphy_vehicle[i];
5295 if (csi2_dphy) {
5296 dcphy_hw->dphy_vehicle[i] = NULL;
5297 dcphy_hw->dphy_vehicle_num--;
5298 break;
5299 }
5300 }
5301 }
5302 /* dphy clks release */
5303 for (i = 0; i < dphy_hw->num_dphy_clks; i++)
5304 clk_put(dphy_hw->dphy_clks[i].clk);
5305 /* dphy rsts release */
5306 if (cif->dphy_hw->chip_id == CHIP_ID_RK3588 ||
5307 cif->dphy_hw->chip_id == CHIP_ID_RK3562) {
5308 for (i = 0; i < dphy_hw->num_dphy_rsts; i++)
5309 reset_control_put(dphy_hw->dphy_rst[i]);
5310 }
5311 /* csi2 clks release */
5312 for (i = 0; i < dphy_hw->num_csi2_clks; i++)
5313 clk_put(dphy_hw->csi2_clks[i].clk);
5314 /* csi2 resets release */
5315 for (i = 0; i < dphy_hw->num_csi2_rsts; i++)
5316 reset_control_put(dphy_hw->csi2_rst[i]);
5317
5318 mutex_destroy(&dphy_hw->mutex);
5319 }
5320
5321 free_irq(cif->irq, cif);
5322 if (inf_id == RKCIF_MIPI_LVDS) {
5323 free_irq(cif->csi2_irq1, cif);
5324 free_irq(cif->csi2_irq2, cif);
5325 }
5326 if (cif->err_state.err_print_wq) {
5327 flush_workqueue(cif->err_state.err_print_wq);
5328 destroy_workqueue(cif->err_state.err_print_wq);
5329 }
5330
5331 return 0;
5332 }
5333